• Title/Summary/Keyword: 2D 터널링

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2D Tunneling Effect of Pocket Tunnel Field Effect Transistor (포켓 구조 터널링 전계효과 트랜지스터의 2D 터널링 효과)

  • Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.243-244
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    • 2017
  • This paper introduces about the difference between the tunneling currents in the 1D and 2D directions for the calculation of the band-to-band tunneling currents of the tunneling field effect transistors. In the two-dimensional tunneling, diagonal tunneling is not calculated in the one-dimensional tunneling so that more accurate tunneling current can be calculated. Simulation results show that the tunneling in the two - dimensional direction has no effect on the voltage above the threshold voltage, but it affects the subthreshold swing below the threshold voltage.

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STM Study of Low Dimensional Nanostructures Formed by Adsorption of Dipyrromethane-trimer Molecules on Graphite Surface (흑연 표면에 형성된 dipyrromethene-trimer 분자의 저차원 나노구조의 주사 터널링 현미경 연구)

  • Son, S.B.;Lee, S.J.;Hahn, J.R.;Shin, J.Y.;Dolphin, D.
    • Journal of the Korean Vacuum Society
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    • v.17 no.5
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    • pp.375-380
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    • 2008
  • We have investigated the low-dimensional nanostructures produced by adsorption of triangular Co coplexed dipyrromethane(DPM-trimer, Fig. 1) on graphite surface by using scanning tunneling microscope. DPM-trimer deposition on the graphite surface leads to the formation of long 1-D molecular wires and 2-D hexagonal patterns. We analyzed the heights and structures of 1-D molecular wires and 2-D hexagonal patterns. The 1-D molecular wires were formed 'edge-on' alignments on graphite surface result of continuos $\pi-\pi$ stacking interactions. The other case of 2-D hexagonal patterns were formed 'face-on' alignments on graphite surface.

$Al/Al_2O_3/Si$(100) Solar Cell 제작 및 특성 평가

  • Min, Gwan-Hong;Yu, Jeong-Jae;Yeon, Je-Min;;Jeong, Sang-Hyeon;Kim, Gwang-Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.313.2-313.2
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    • 2013
  • 본 연구에서는 기존에 연구된 Solar Cell 보다 구조 및 제작이 단순한 $Al/Al_2O_3/Si$(100) Solar cell을 제작하여 평가하였다. 기판으로는 p-type Si(100), 0.5~2 ${\Omega}{\cdot}cm$을 사용하여 chemical cleaning 후 ALD(Atom Layer Deposition)법으로 Al2O3 터널링 절연막을 증착하였으며, 박막의 두께를 1~10 nm로 변화시켜 MIS 커패시터의 터널링 효과를 평가하였다. MIS 커패시터의 전기적 특성평가를 위해 누설전류 밀도-전계 특성은 pA meter/DC Voltage source를 사용하였고, 커패시턴스-전압특성, D-factor 특성은 precision LCR meter를 사용하였다. $Al/Al_2O_3/Si$(100) Solar cell의 특성평가를 위해 300~1100nm 파장영역에 따른 양자 효율을 평가하기 위해 Quantum Efficiency system (QE)을 사용하였고, Stanard Test Conditions 100 $mW/cm^2$, AM1.5, $25^{\circ}C$ 조건의 Voc, Isc, Jsc, FF (Fill Factor) 및 Efficiency(%)를 평가하기 위해 Solar simulator를 이용하였다.

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Performance and SILC Characteristics of Flash Memory Cell With Ultra thin $N_2O$ Annealed Tunneling Oxide (초박막의 $N_2O$ 어닐링한 터널링 산화막을 갖는 Flash Memory Cell의 SILC 특성 및 성능)

  • Son, Jong-Hyoung;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.10
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    • pp.1-8
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    • 1999
  • In this paper, we have studies the transport mechanism and origin of SILC for the various thickness of wet oxide. Also, SILC characteristics of $N_2O$ annealed oxide was included in this study. We made the flash memory cell with $N_2O$ annealed oxide of 60Athick under $0.25{\mu}m$ design rule, and measured the characteristics of the cell. As a result, we have found that the origin of SILC is due to the trap formed inside of the oxide layer by electrical stress. And we reached the conclusion that the transport mechanism of SILC is ruled by the modified F-N tunneling if the electric field is lower than 8MV/cm or typical F-N tunneling if the electric field is higher than 8MV/cm. We could also confirm the fact that $N_2O$ annealed oxide of 60Athick have an improved resistance effect against SILC. In case that we apply $N_2O$ annealed oxide of 60Athick to the flash memory, we could confirm $10^6$ times endurance and more than 10 years drain disturb, and could get 8V programmable flash memory characteristics.

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Study of monolithic 3D integrated-circuit consisting of tunneling field-effect transistors (터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구)

  • Yu, Yun Seop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.5
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    • pp.682-687
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    • 2022
  • In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

Investigation on the Doping Effects on L-shaped Tunneling Field Effect transistors(L-shaped TFETs) (도핑효과에 의한 L-shaped 터널링 전계효과 트랜지스터의 영향에 대한 연구)

  • Shim, Un-Seong;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.450-452
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    • 2016
  • The effect of channel doping on L-shaped Tunneling Field-Effect Transistors (TFETs) have been investigated by 2D TCAD simulation. When the source doping is over $10^{20}cm^{-3}$, the subthreshold swing (SS) is abruptly decreased, and when drain doping concentration is below $10^{18}cm^{-3}$, the leakage current in the negative voltage is reduced.

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Tunneling Density of States in Superconductor/d-wave Superconductor Proximity Junction (초전도체와 d-wave 초전도체 근접효과 접합에서의 터널링 상태밀도함수)

  • Lee, H. J.;Yonuk Chong;J. I. Kye;Lee, S. Y.;Z.G. Khim
    • Progress in Superconductivity
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    • v.2 no.2
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    • pp.57-64
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    • 2001
  • We have calculated the tunneling density of states (TDOS) of a metal/d-wave superconductor proximity junction, where the metal stands fur the normal metal, 5-wave superconductor, and d-wave superconductor. The tunneling direction is through the ab-plane of the d-wave superconductor. Because of the sign change in the order parameter experienced in the multiple Andreev reflection, there appears a finite TDOS at zero bias for duty geometry, which results in the anomalous zero bias conductance peak(ZBCP). For $d_{x2-y2}$ geometry, however, no TDOS peak appears at zero bias. We have calculated TDOS for various crystal orientation of HTSC and compared with the experimental conductance.

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Influence on Short Channel Effects by Tunneling for Nano structure Double Gate MOSFET (나노구조 이중게이트 MOSFET에서 터널링이 단채널효과에 미치는 영향)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.3
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    • pp.479-485
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    • 2006
  • The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

Inelastic Electron Tunneling in Au/polyimide/monolayer Organic Film/Pb Structures using a Polyimide Barrier (Polyimide 터널 장벽을 이용한 Au/polyimide/유기 단분자막/Pb 구조에서 비탄성 전자 터널링에 관한 연구)

  • ;;;;;;M. Iwamoto
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.2
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    • pp.196-200
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    • 2004
  • Using polyimide Langmuir-Blodgett(LB) films as a tunneling harrier, we fabricated Au/Polyimide/1-layer arachidic acid/Pb structure in order to investigate electron transport properties through a junction. It was found that 9-layer polyimide LB films function as a good tunneling harrier in a study of current-voltage(I-V) chararteristics. And several peaks originating in the vibrational modes of the constituent molecules of 1-layer arachidic acid LB films were clearly observed in d$^2$V/dI$^2$- V corves.

A Study of Smoke Movement in Tunnel Fires (터널내에서 화재 발생시 연기 거동에 대한 연구)

  • 김상훈;김성찬;김충익;유홍선
    • Fire Science and Engineering
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    • v.14 no.2
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    • pp.21-32
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    • 2000
  • In this study, reduced-scale experiments as the alternative to a real-scale fire test were conducted to understand fire properties in tunnel, and their results were compared with those of numerical simulation. The 1/20 scale experiments were conducted under the Froude scaling since smoke movement in tunnel is governed by buoyancy farce. A numerical simulations were on performed 3D unstructured meshes with PISO algorithm and buoyant plume models. Results showed that data was in reasonable agreement with the numerical data of smoke velocity, temperature distribution, and clear height.

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