• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.2
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• pp.257-262
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• 2012

The Ministry of Information-Communication assigned 18~19GHz frequency band for communication of cabins and platform to link between subway/train and it's station. In this paper, we propose wireless transmission devices which are 2 stage hybrid low noise amplifier of 18GHz band and mixer for 18GHz as well to apply for RF receiver. We designed LNA to be noise matched its 1st stage and gain matched for 2nd stage and mixer using $180^{\circ}$ hybrid coupler to suppress the spurious signal. The transistors of 18 GHz LNA and mixer are NE3210S01 of NEC and KMB-N51-1, respectively. As the result of simulation, we get 19.92dB gain and 2.06dB noise figure with LNA and 8.61dB conversion loss with mixer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.102-109
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• 2000

In this paper, a Low Noise Amplifier for B-WLL was designed using the MMIC technology with GaAs PHEMTs fabricated at our lab. The PHEMT for LNA has a $0.35\mu\textrm{m}$ gate and a total gate width of $120\mu\textrm{m}$. The designed MMIC LNA consists of three stages. The first stage of the LNA has a series inductive feedback for obtaining minimum noise and high stability as well. And the designed MMIC LNA has not an interstage matching circuit between the second and the third stage for minimization of the chip size. From simulation results, noise figure and S21 gain of the designed MMIC LNA are 0.85~1.25 dB and 22.08~23.65 dB in the frequency range of 25.5~27.5 GHz respectively. And the chip size is $3.7\times1.6 mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.54-61
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• 2007

A variable gain low noise amplifier (VG-LNA) implemented in TSMC 0.18 um process is presented. This VG-LNA is designed of two stage amplifier, and its gain is controlled by the shunt feedback loop composed of a gain control transistor (GCT) and a coupling capacitor in second stage. The channel resistance of GCT in the shunt feedback loop influences the input and output stages of a second stage by the Miller effect. Total gain of the proposed VG-LNA is changed by two factors, the load impedance reduction and the interstage mismatch by controlling the channel resistance of the GCT. Consequently, by adding a shunt feedback with a gain control transistor, this proposed VG-LNA achieves both wide gain tuning range of 37 dB and continuous gain control simultaneously.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.443-447
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• 2005

In this paper, a low noise amplifier(LNA) in a receiver of a Low Noise Block Down Converter (LNB) for direct broadcasting service(DBS) is implemented using GaAs HEMT. The 2-stage LNA is designed for the bandwidth of 11.7GHz - 12.2GHz. The result of a simulation of the LNA using Advanced Design System(ADS) shows that the noise figure is less than 1.4dB, the gain is greater than 23dB and the flatness is 1dB in the bandwidth of 11.7 to 12.2GHz.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.48-51
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• 2009

One-stage low noise amplifier (LNA) using 65 nm RF CMOS technology below 20 GHz is designed to find the optimal bias voltage and optimal width of input transistor so that the maximum figure of merit (FoM) has been achieved. If the frequency is higher than 13 GHz, the amplifier needs two-stage to achieve the higher gain. If the frequency is lower than 5 GHz, one additional capacitor between gate and source should be added to control the power under the limitation. This paper summarizes one-stage LNA overall performances below 20 GHz and this approach can also be applied to other CMOS technology of LNA designs.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.319-322
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• 1998

A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.289-294
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• 2008

A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1137-1140
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• 2002

A V-band low-noise amplifiers (LNA) based on the Millimeter-wave monolithic integrated circuit (MIMIC) technology were fabricated using high performance 0.1 $\mu\textrm{m}$ $\Gamma$-shaped pseudomorphic high electron mobility transistors (PHEMT＇s), coplanar waveguide (CPW) structures and the integrated process for passive and active devices. The low-noise designs resulted in a two-stage MIMIC LNA with a high S$\sub$21/ gain of 14.9 dB and a good matching at 60 ㎓. 20 dBm of IP3 and 3.9 dB of minimum noise figure were also obtained from the LNA. The 2-stage LNA was designed in a chip size of 2.3 ${\times}$1.4 mm$^2$by using 70 $\mu\textrm{m}$ ${\times}$2 PHEMT’s. These results demonstrate that a good low-noise performance and simultaneously with a high gain performance is achievable with GaAs PHEMT's in the 60 ㎓ band.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.54-59
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• 2008

In this paper, circularly polarized patch antenna with 2-stage LNA for the reception of S-DMB is presented. It used teflon didelectric substrate of ${\in}_r$=2.2 and the size is $40{\times}40{\times}15\;[mm]$. Experimental results of fabricated antenna show that bandwidths of input return loss and axial ratio are about 22 [MHz] and 25 [MHz]. Input return loss, output return loss, gain, and noise figure of the fabricated 2-stage LNA are $S_{11}$=-14 [dB], $S_{22}$=-18 [dB], $S_{21}$=26.8 [dB], and NF=1.14 [dB] respectively. The fabricated active type antenna has total gain of 30.4 [dB] at 2.642 [GHz].