• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• Convergence Security Journal
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• v.20 no.5
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• pp.3-10
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• 2020

Recently, the Internet and networks are regarded as essential infrastructures that constitute society, and security threats have been constantly increased. However, the network switch that actually transmits packets in the network can cope with security threats only through firewall or network access control based on fixed rules, so the effective defense for the security threats is extremely limited in the network itself and not actively responding as well. In this paper, we propose an in-network security framework using the high-level data plane programming language, P4 (Programming Protocol-independent Packet Processor), to deal with DDoS attacks and IP spoofing attacks at the network level by monitoring all flows in the network in real time and processing specific security attack packets at the P4 switch. In addition, by allowing the P4 switch to apply the network user's or administrator's policy through the SDN (Software-Defined Network) controller, various security requirements in the network application environment can be reflected.

• Journal of the Korea Society of Computer and Information
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• v.9 no.4 s.32
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• pp.173-178
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• 2004

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR. ABR) generated by a wide range of services ATM services the Quality-of-Service (QoS) management of traffice sources and bandwidth. Besides efficiency and throughput, the security services are achieved in the traffic sent in ATM network. In this paper, the scheduler evaluate and the packets sent in ATM security group. The scheduler transmits the safty packet, drop the unsafty packet and evaluate mark packet as the requirement of the delay. In this paper, we propose the scheduling algorithm of mark packet which evaluates the packet. The suggested model performance of the firewall switch is estimate simulation in terms of the delay by computer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.642-646
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• 2004

시스템 패킷 인터페이스 4레벨 2단계(System Packet Interface Leve1 4 Phase 2)는 10Gbps 이더넷 응용뿐만 아니라, OC-192 대역폭의 ATM 및 POS를 통한 패킷 또는 셀 전송을 위한 물리계층과 링크계층 소자간의 인터페이스이다. 본 논문에서는 시스템 패킷 인터페이스 4레벨 2단계(SPI-4.2)에 대한 연구와 C언어를 이용한 성능평가를 토대로 모듈을 VHDL언어를 이용하여 설계하였다. 성능평가시 확인된 짧은 패킷이 유입되었을 때 PCW와 다음 PCW의 거리를 16바이트 이상을 유지하기 위해 ICW가 삽입되어 많은 오버헤드를 발생시켰다. 작은 패킷이 유입되었을 때 오버헤드를 최소화하기 위해 ICW생성을 최대한 제한하게 설계하여 짧은 패킷 유입시의 오버헤드를 감소하는 SPI-4.2 인터페이스 수신부 모듈을 설계하였다. 설계한 모듈은 라인당 720Mbps를 지원하여 총 대역폭이 11.52Gb/s의 전송률을 나타내어 더욱 안정적으로 패킷을 인터페이스 할 수 있다. XilinxISE 5.1i 툴을 이용하여 VHDL언어로 설계하였고, Model_SIM 5.6a를 이용하여 시뮬레이션 하였다. SPI-4.2 인터페이스 모듈은 기가비트/테라비트 라우터, 광학 크로스바 스위치 및 SONET/SDH 기반의 수신 시스템에서 라인카드로 사용할 경우 적합할 것으로 사료된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.291-294
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• 2004

In this paper, we consider the broadcast switch architecture for hish performance multicast packet switching. In input and output buffered switch, we propose a new switch architecture which supports high throughput in broadcast packet switching with switch planes of single input and multiple output crossbars. The proposed switch architecture has a central arbiter that arbitrates requests from plural input ports and generates multiple grant signals to multiple output ports in a packet transmission slot. It provides high speed pipelined arbitration and large scale switching capacity.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.738-748
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• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• Journal of KIISE:Information Networking
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• v.36 no.1
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• pp.57-67
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• 2009

Packet forwarding in the Internet routers is to find out the longest prefix that matches the destination address of an input packet and to forward the input packet to the output port designated by the longest matched prefix. The IP address lookup is the key of the packet forwarding, and it is required to have efficient data structures and search algorithms to provide the high-speed lookup performance. In this paper, an efficient IP address lookup algorithm using binary search is investigated. Most of the existing binary search algorithms are not efficient in search performance since they do not provide a balanced search. The proposed binary search algorithm performs perfectly balanced binary search using switch pointers. The performance of the proposed algorithm is evaluated using actual backbone routing data and it is shown that the proposed algorithm provides very good search performance without increasing the memory amount storing the forwarding table. The proposed algorithm also provides very good scalability since it can be easily extended for multi-way search and for large forwarding tables

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.399-401
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• 1999

최근 컴퓨터 네트워크를 통한 화상회의, 화상전화 VOD 등과 같은 응용 프로그램들이 실시간 통신을 필요로 한다. 이러한 실시간 통신에 적합한 ATM은 유연한 통신 서비스와 높은 질의 서비스를 제공함으로서 차세대 통신 네트웍으로 기대가 되고 있다. ATM 네트웍 막에서 실시간 통신을 하기 위해서는 실시간 데이터들이 지연한계를 만족해야 한다. 만약 이러한 지연한계를 만족시키지 못할 경우에는 서비스의 질이 떨어지거나 아니면 데이터가 아예 필요가 없어지게 된다. 이미 실시간 통신을 하기 위해 Virtual Clock, Stop-and-Go, EDF 등에 많은 패킷 스위치 스케줄링 정책들이 개발 되어져 왔다. 그러나 이러한 스위치 스케줄링 정책들은 대부분 그 방법의 복잡성 때문에 실제로 ATM 상에서 적용시키기가 힘들다. 본 논문에서는 ATM 네트웍 망에서 화상 통신을 하기 위해 적합한 새로운 스위치 모델인 TCRM-DS를 제시한다. TCRM-DS는 기존의 TCRM 모델의 장점인 단순성과 효율성을 그대로 유지하면서 TCRM 모델의 단점인 비 실시간 데이터에 대한 비효율적 처리를 개선한 것이다.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.193-202
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• 2007

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches under Hot-spot environment is proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch. The performance of the multiple-buffered $a{\times}a$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes. Two important parameters of the network performance, throughput and delay, are then evaluated. To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1631-1642
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• 1999

In this paper, we propose a new fault tolerant ATM Switch and a new adaptive self-routing scheme used to make the switch to be fault tolerant. It can provide more multiple paths than the related previous switches between an input/output pair of a switch by adding extra links between switching elements in the same stage and extending the self-routing scheme of the Banyan network. Our routing scheme is as simple as that of the banyan network, which is based on the topological relationships among the switching elements (SE’s) that render a packet to the same destination with the regular self-routing. These topological properties of the Banyan network are discovered in this paper. We present an algebraic proof to show the correctness of this scheme, and an analytic reliability analysis to provide quantitative comparisons with other switches, which shows that the new switch is more cost effective than the Banyan network and other augmented MIN’s in terms of the reliability.