• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.327-332
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• 2012

In this paper, we analyzed the influence of different observation stations distributions on satellite clock offset estimation based on the PANDA software. The result shows that, when the distance between stations is shorter than 200km, the correlation of troposphere parameter and satellite clock offset parameter is strong, the accuracy of satellite clock offset estimation will be up to 0.8ns; when the distance between stations is up to 500km, as the correction of troposphere parameter and satellite clock offset parameter is significantly reduced, and the two kinds of parameters can be distinguished.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.07a
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• pp.69-72
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• 2013

본 논문은 TPSN 알고리즘의 시각 동기화 오차를 개선하기 위하여 Imote2 센서 노드의 클럭 드리프트 특성을 적용하는 개선된 TPSN 알고리즘을 제안한다. 클럭 드리프트의 원인은 주로 수정발진기에 기인한다. 본 연구에서는 온도 및 습도 등 환경 조건이 비슷할 경우에 드리프트가 크게 차이나지 않는다는 실험 결과에 따라 드리프트의 평균값을 구하고 이를 TPSN 동기화 오차 보정에 사용한다. 이때 적용되는 드리프트 특성 값은 센서 노드 설치 이전에 미리 측정하여야 한다. 실험을 통하여 본 논문에서 제안한 개선된 TPSN 알고리즘이 동기화 오차 개선에 효과적임을 확인하였다.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.227-236
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• 2005

We study, in terms of VoIP user assessment of voice quality, the synchronization of measurement system is important. Commonly the synchronization system uses NTP(Network Time Protocol) or GPS(Global Positioning System), these synchronization method has time error of distance, system overhead of data processing, and system specialized clock error. we propose and implement the synchronization method to correct time error between two measurement system in the internet. So the time synchronization of systems can get time error, then user assessment of voice quality become reliable.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.93-97
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• 2007

In this paper a new clock generation scheme for TDM-CDM converter in the Gap Filler for satellite DMB systems has been proposed. The scheme uses the frame sync signal from the Ku band TDM receiver to lock the VCXO which provides the system clock for the TDM-CDM converter. The locking algorithm can be easily implemented in the FPGA, so that no separate circuitry is needed as in conventional PLL. With a stable OCXO, The scheme can be used to generate the reference clock to the local oscillator for RF parts.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.235-244
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• 2000

This paper presents a low power PLL based clock geneator circuit for microprocessors. It generates 32MHz${\sim}$1GHz clocks and can be integrated inside microprocessor chips. A high speed D Flip-Flop is designed using dynamic differential latch and a new Phase Frequency Detector(PFD) based on this FF is presented. The PFD enjoys low error characteristics in phase sensitivity and the PLL using this PFD has a low phase error. To improve the linearity of voltage controlled oscillator(VCO) in PLL, the voltage to current converter and current controlled oscillator combination is suggested. The resulting PLL provides wide lock range and extends frequency of generated clocks over 1 GHz. The clock generator is designed by using $0.65\;{\mu}m$ CMOS full custom technology and operates with $11\;{\mu}s$ lock-in time. The power consumption is less than 20mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.