• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.310-310
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• 2012

최근 전자산업의 발달에 따른 전자제품의 소형화 및 고기능화 요구에 대응하기 위하여 저항(resistor), 커패시터(capacitor), IC (integrated circuit) 등의 수동소자를 개별 칩(discrete chip) 형태로 형성하여 기판의 표면에 실장하는 기술이 일반화되고 있다. 그러나, 수동 소자의 내장 기술은 기판의 패턴 밀도의 급격한 향상과 더불어 수동소자의 내장 공간도 협소해지는 문제점이 있다. 상기의 문제점을 해결하기 위해 개별 칩 형태의 내장형 저항체를 박막 형태의 내장 저항체를 구현하는 기술의 개발이 최근 주목을 받고 있다. 박막 저항체는 기존의 권선저항 및 후막저항과 비교하여 정밀한 온도저항계수를 가지며 이동통신에 적용시 고주파 영역(GHz)에서의 안정성과 주파수 특성이 좋다는 장점들을 가지고 있다. 박막 저항 물질로는 높은 경도와 우수한 열적 안정성을 가지고 있는 TaN (tantalum nitride)이 주로 사용되고 있다. 일반적으로, TaN 박막은 스퍼터링을 사용하며 제조되며 TaN 박막의 성질은 탄탈륨과 질소의 화학정량비, 박막의 결함 정도, 또는 공정압력 및 증착 온도, 플라즈마 파워 등과 같은 공정조건 등의 변화에 민감하게 변화하므로, TaN 박막의 다양한 연구가 더 필요한 실정이다. 본 연구에서는 반응성 마크네트론 스퍼터링을 사용하여 TaN 박막을 Si 기판 위에 증착하였고 TaN 박막의 원하는 특성을 제어할 수 있도록 질소 분압과 total gas volume을 조절하여 공정을 최적화하는 연구를 진행하였다. 또한 tensile pull-off 방법을 이용하여 TaN 박막의 부착강도를 평가하였고, 온도 사이클 및 고온고습 환경에 노출된 TaN 박막들의 열화 특성들에 대하여 연구하였다.

• Korean Journal of Optics and Photonics
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• v.24 no.6
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• pp.342-346
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• 2013

We present the thermal analysis result of die bonding for a high power LED package using a metal hybrid silicone adhesive structure. The simulation structure consists of an LED chip, silicone die adhesive, package substrate, silicone-phosphor encapsulation, Al PCB and a heat-sink. As a result, we demonstrate that the heat generated from the chip is easily dissipated through the metal structure. The thermal resistance of the metal hybrid structure was 1.662 K/W. And the thermal resistance of the total package was 5.91 K/W. This result is comparable to the thermal resistance of a eutectic bonded LED package.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.203-211
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• 2013

UHF RFID tag designers usually ndde the chip impedance and read power sensitivity value obtained when a tag chip is mounted on a chip pad. The chip impedance, however, is not able to be supplied by chip manufacturer, since the chip impedance is varied according to tag designs and fabrication processes. Instead, the chip makers mostly supply the chip impedances measured on the bare dies. This study proposes a chip impedance and read power sensitivity evaluation method which requires a few simple auxiliary and some RF measuring equipment. As it is impractical to measure the chip impedance directly at mounted chip terminals, some form test fixture is employed and the effect of the fixture is modeled and de-embeded to determine the chip impedance and the read power sensitivity. Validity and accuracy of the proposed de-embed method are examined by using commercial RFID tag chips as well as a capacitor and a resistor the value of which are known.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.5
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• pp.716-723
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• 2002

Heat transfer in linear motor driven stages for surface mounting device applications was investigated. A simple one-dimensional thermal resistance model (TRM) was introduced. In order to reduce three-dimensional nature to one-dimensional, a few assumptions and simplifications were employed suitably. A good agreement with a finite element heat transfer analysis in temperature profile was obtained. For validation, the analysis was compared with the measurement with respect to motor driving power. Overall discrepancy was less than 7$^{\circ}C$. The influence of two high thermal resistance parts, insulation sheet and thermal contact between the coil assembly and the mounting plate, was examined through the analysis. Additionally, the thermal resistance analysis was applied to another stage including an internal cooling-air passage, and was found available for this system as well. After validation, the cooling effect was surveyed in terms of motor power, and cooling-air and -water flow rate.

• Proceedings of the KSME Conference
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• 2001.11b
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• pp.96-101
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• 2001

Heat transfer in linear motor driven stages for surface mounting device applications was investigated. A simple one-dimensional thermal resistance model was introduced. In order to reduce three-dimensional nature to one-dimensional, a few assumptions and simplifications were employed suitably. A good agreement with a finite element heat transfer analysis in temperature profile was obtained. For validation, the analysis was compared with the measurement with respect to motor driving power. Overall discrepancy was less than $7^{\circ}C$. The influence of two high thermal resistance parts, insulation sheet and thermal contact between the coil assembly and the mounting plate, was examined through the analysis. Additionally, the thermal resistance analysis was applied to another stage including an internal cooling-air passage, and was found available for this system as well. After validation, the cooling effect was surveyed in terms of motor power, and cooling-air flow rate.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.133-135
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• 2005

Mn-Co-Ni-O계를 적용한 적층 칩 NTC 써미스터의 소성온도 및 냉각 조건에 따른 전기적 특성을 연구하였다. 특히, 소결조건에 따른 저항, B-정수의 경시 변화 특성으로부터 제품의 신뢰성 측면을 검토하였다. 소결온도 및 시간에 의한 영향보다는 냉각속도에 따른 초기 저항 및 B-정수의 변화가 크게 나타났으며 냉각속도를 조절한 시편에서 경시변화율은 1%이하인 특성을 얻을 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.9-17
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• 2008

Cu mushroom bumps were formed by electrodeposition and flip-chip bonded to Sn substrate pads. Contact resistances of the Cu-mushroom-bump joints were measured and compared with those of the Sn-planar-bump joints. The Cu-mushroom-bump joints, processed at bonding stresses ranging from 19.1 to 95.2 MPa, exhibited contact resistances near $15m\Omega$/bump. Superior contact-resistance characteristics to those of the Sn-planar-bump joints were obtained with the Cu-mushroom-bump joints. Contact resistance of the Cu-mushroom-bump joints was not dependent upon the thickness of the as-elecroplated Sn-capcoating layer ranging from $1{\mu}m$ to $4{\mu}m$. When the Sn-cap-coating layer was reflowed, however, the contact resistance was greatly affected by the thickness and the reflow time of the Sn-cap-coating layer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.1
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• pp.24-29
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• 2006

A new oscillatory neural circuit with computational function has been designed and been designed and fabricated in an $0.5{\mu}m$ double poly CMOS technology. The proposed oscillatory circuit consists of 3 neural oscillators with excitatory synapses and a neural oscillator with inhibitory synapse. The oscillator block which is a basic element of the neural circuit is designed with a variable negative resistor and 2 transconductors. The variable negative resistor which is used as a input stage of the oscillator consist of a bump circuit with Gaussian-like I-V curve. SPICE simulations of a designed neural circuit demonstrate cooperative computation. Measurements of the fabricated neural chip in condition of ${\pm}$ 2.5 V power supply are shown and compared with the simulated results.