Flip Chip Process by Using the Cu-Sn-Cu Sandwich Joint Structure of the Cu Pillar Bumps

Cu pillar 범프의 Cu-Sn-Cu 샌드위치 접속구조를 이용한 플립칩 공정

  • Choi, Jung-Yeol (Department of Materials Science and Engineering, Hongik University) ;
  • Oh, Tae-Sung (Department of Materials Science and Engineering, Hongik University)
  • Published : 2009.12.30

Abstract

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

Cu pillar 범프를 사용한 플립칩 기술은 솔더범프를 사용한 플립칩 공정에 비해 칩과 기판 사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하다는 장점이 있다. Cu pillar 범프를 사용한 플립칩 공정은 미세피치화와 더불어 기생 캐패시턴스를 억제하기 위해 칩과 기판 사이에 큰 거리가 요구되는 RF 패키지에서도 유용한 칩 접속공정이다. 본 연구에서는 Sn 캡을 형성한 Cu pillar 범프와 Sn 캡이 없는 Cu pillar 범프를 전기도금으로 형성한 후 플립칩 접속하여 Cu-Sn-Cu 샌드위치 접속구조를 형성하였다. Cu pillar 범프 상에 Sn 캡의 높이를 변화시키며 전기도금한 후, Sn 캡의 높이에 따른 Cu-Sn-Cu 샌드위치 접속구조의 접속저항과 칩 전단하중을 분석하였다. 직경 $25\;{\mu}m$, 높이 $20\;{\mu}m$인 Cu pillar 범프들을 사용하여 형성한 Cu-Sn-Cu 샌드위치 접속구조에서 $10{\sim}25\;{\mu}m$ 범위의 Sn 캡 높이에 무관하게 칩과 기판 사이의 거리는 $44\;{\mu}m$으로 유지되었으며, 접속부당 $14\;m{\Omega}$의 평균 접속저항을 나타내었다.

Keywords

References

  1. J. H. Choi, K. Y. Lee, S. W. Jun, Y. H. Kim, and T. S. Oh, "Contact Resistance of the Chip-on-glass Bonded 48Sn-52In Solder Joint", Mater. Trans., 46, 1042-1046 (2005). https://doi.org/10.2320/matertrans.46.1042
  2. J. W. Wan, W. J. Zhang, and D. J. Bergstrom, "Recent Advances in Modeling the Underfill Process in Flip-chip Packaging" Microelectron. J., 38, 67-75 (2007). https://doi.org/10.1016/j.mejo.2006.09.017
  3. T. Braun, K. F. Becker, M. Koch, V. Bader, R. Aschenbrenner, and H. Reichl, "High-temperature Reliability of Flip Chip Assemblies", Microelectron. Reliab., 46, 144-154 (2006). https://doi.org/10.1016/j.microrel.2005.06.004
  4. K. N. Tu and K. Zeng, "Under Bump Metallurgy Study for Pb-free Bumping", Mater. Sci. Eng., 34, 1-58 (2001). https://doi.org/10.1016/S0927-796X(01)00029-8
  5. J. H. Lau, Low Cost Flip Chip Technologies, pp.511, McGraw-Hill, New York (2000).
  6. J. H. Lau, Low Cost Flip Chip Technologies, pp.183, McGraw-Hill, New York (2000).
  7. U. B. Kang and Y. H. Kim, "A New COG Technique Using Low Temperature Solder Bumps for LCD Driver IC Packaging Applications", IEEE Trans. Comp. Packag. Technol., 27, 253-258 (2004). https://doi.org/10.1109/TCAPT.2004.828585
  8. J. W. Kim, Y. C. Lee, and S. B. Jung, "Effect of Bonding Conditions on Conduction Behavior of Anisotropic Conductive Film Interconnection", Met. Mater. Int., 14, 373-380 (2008). https://doi.org/10.3365/met.mat.2008.06.373
  9. B. Banijamali, I. Mohammed, and P. Savalia, "Crack Growth-Resistant Interconnects for High-Reliability Microelectronics" Proc. 57th Electron. Comp. Technol. Conf., pp.1880-1886 (2008).
  10. A. Keigler, B. Wu, J. Zhang, and Z. Liu, "Pattern Effects on Electroplated Copper Pillars", Inter. Wafer-level Packag. Conf. (2006).
  11. G. T. Lim, B. J. Kim, K. Lee, J. Kim, Y. C. Joo, and Y. B. Park, "Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps", J. Electron. Mater., 38(11), 2228-2233 (2009). https://doi.org/10.1007/s11664-009-0922-0
  12. T. Wang, F. Tung, L. Foo, and V. Dutta, "Studies on a Novel Flip-Chip Interconnect Structure-Pillar Bump", Proc. Electron. Comp. Technol. Conf., pp.945-949 (2001).
  13. L-R. Zheng, X. Duo, M. Shen, W. Michielsen, and H. Tenhunen, "Cost and Performance Trade-off Analysis in. Radio and Mixed-Signal System-on-Package Design", IEEE Trans. Adv. Packag., 27, 364-375 (2004). https://doi.org/10.1109/TADVP.2004.828818
  14. A. Chandrasekhar, E. Beyne, W. Raedt, and B. Nauwelaers, "Accurate RF Electrical Characterization of CSPs Using MCM-D Thin Film Technology", IEEE Trans. Adv. Packag., 27, 203-212 (2004). https://doi.org/10.1109/TADVP.2004.824945
  15. E. Beyne, "Multilayer Thin-Film Technology Enabling Technology for Solving High-Density Interconnect and Assembly Problems", Nuclear Inst. Methods Phys. Res. A, 509, 191-199 (2003). https://doi.org/10.1016/S0168-9002(03)01570-5
  16. J. Y. Choi, M. Y. Kim, S. K. Lim, and T. S. Oh, "Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps" J. Korean Microelectron. Packag. Soc., 16, 33-40 (2009).
  17. C. W. Tan, Y. C. Chan, and N. H. Yeung, "Effect of Autoclave Test on At sotropic Conductive Jointf, Microelectron. Reliab., 43, 279-285 (2003). https://doi.org/10.1016/S0026-2714(02)00293-7
  18. J. H. Zhang, Y. C. Chan, M. O. Alam, and S. Fu, "Contact Resistance and Adhesion Performance of ACF Interconnections to Aluminum Metallization", Microelectron. Reliab., 43, 1303-1310 (2003). https://doi.org/10.1016/S0026-2714(03)00165-3
  19. Y.-T. Hsieh, "Reliability and Failure Mode of Chip-on-film with Non-conductive Adhesive", Proc. Int. Symp. Electron. Mater. Packag., pp.157-160 (2002).