• Korean Chemical Engineering Research
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• v.58 no.2
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• pp.319-324
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• 2020

Electroconvective instability is a non-linear transport phenomenon which can be found in ion-selective transport system such as electrodialysis, Galvanic cell and electrolytic cell. The instability is triggered by the fluctuation of space charge layer in adjacent of ion-selective surface, leading to increase of mass transport rate. Thus, in the aspect of mass transport, the instability has an important meaning. Although recent experimental techniques have opened up an avenue to direct visualize the instability, fundamental investigations have been conducted in limited area due to several experimental limitations. In this work, the electroconvective instability under potentiostatic mode was solved by numerical method in order to demonstrate correlation between current-time curve and the instability behavior. By rigorous time-resolved analysis, the transition behaviors can be divided into three stages; formation of space charge layer - growth of electroconvective instability - steady state. Furthermore, scaling laws of transition time were numerically obtained according to applied voltage as well.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05b
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• pp.73-75
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• 2004

Resistive leakage current following arresters is an important indicator of ageing, but total leakage current and its harmonic analysis are widely used in diagnosing arrester soundness because of difficulties in measuring resistive leakage current. In this paper, we proposed a new method for measuring resistive leakage current, which is quite different from the conventional methods such as a self-cancel method and a synchronous rectification method. The proposed method is based on that the magnitudes of resistive leakage currents are equal at the same voltage level. To confirm the possibility of the proposed method. we fabricated a leakage current measurement device and designed an analysis program that can analyze resistive leakage current. Comparing with other methods. this technique does not need a complex circuitry and is very simple to complete.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.2
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• pp.58-67
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• 1995

The paper describes the variation of magnetic fields caused by the operation of induction motors. The measuring system consists of the self-integrating magnetic field sensor, amplifier, and active integrator. From the calibration experiments, the frequency bandwidth of the magnetic field measuring system ranges from 20[Hz] to 300[kHz] and sensitivity is 0.234(mV/$\mu\textrm{T}$]. The magnetic fields generated under steady state and starting operations of duction motor are recorded by the proposed measuring system, and the fast Fourier transformation(FFT) of the measured data is performed to analyze the harmonic components. A single pulsed magnetic field is strongly caused by direct starting the induction motor, and its peak value is greater than 5 times as compared with the steady state value. The long transient duration and high intensity originates from the large inductance and dynamic characteristic of the induction motor, During the steady state operation of induction motor, subharmonics of magnetic field components, which depend on the pole number of induction motor, are observed. The lower order power-line harmonics can be inferred from the voltage flicker and current ripple which are derived from the torque fluctuation of induction motor. In the case of the induction motor drived by inverter, the harmonics of magnetic field are much more than those caused by direct starting method and are found generally to increase with decreasing the driving frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.8 no.4
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• pp.23-32
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• 1988

The rates of infiltration contributed to the flow fo water in an unconfined aquifer under the partially penetrated stream at an ungaged station and the corresponding base flow in channel are coupled by using the hydraulic and/or hydrologic characteristics obtained from the geomorphologic and soil maps. For the determination of groundwater flow, the linearized model which is originally Boussinesq's nonlinear equation is applied in this study. Also, a stream flow routing model for base flow in channel is based on a simplification of the Saint-venant. The distributed runoff model with piecewise spatial uniformity is presented for obtaining its solution based on a finite difference technique of the kinematic wave equations. The method developed in this study was tested to the Bocheong watershed(area : $475.5km^2$) of the natural stream basin which is one of tributaries in Geum River basin in Korea. As a result, it is suggested that the rationality of hydro-graph separation according to a wide variability in hydrogeologic properties be worked out as developing the physically based subsurface model. The results of the present model are shown to be possible to simulate a base flow due to an arbitrary rate of infiltration for ungaged basins.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.53-53
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• 1999

전계방출을 이용한 평판 표시장치는 CRT가 가진 장점을 모두 갖는 동시에 얇고 가벼우며 낮은 전력소모로 완벽한 색을 구현할 수 있는 차세대 표시장치로서 이에 대한 여국가 활발히 이루어지고 있다. 여기에 사용되는 음극물질로서 실리콘이나 몰리 등을 팁모양으로 제작하여 사용해 왔다. 하지만 잔류가스에 의한 역스퍼터링이나 화학적 반응에 의해서 전계방출 성능이 점차 저하되는 등의 해결해야할 많은 문제가 있다. 이러한 문제들을 해결하기 위하여 탄소계 재료로서 다이아몬드, 다이아몬드상 카본 등을 이용하려는 노력이 진행되어 왔다. 이중 유리화 비정형 탄소는 다량의 결함을 가지고 있는 유리질의 고상 탄소 재로로서, 전기전도도가 우수하면서 outgassing이 적고 기계적 강도가 뛰어나며 고온에서도 화학적으로 안정하여 전계방출 소자의 음극재료로서 알맞은 것으로 생각된다. 유리화 비정형 탄소가루를 전기영동법으로 기판에 코팅하여 전계방출 소자를 제작하였다. 전기영동 용액으로 이소프로필알코올에 질산마그네슘과 소량의 증류수, 유리화 비정형 탄소분말을 섞어주었고 기판으로는 몰리(Mo)가 증착된 유리를 사용하였다. 균일한 증착을 위해서 증착후 역전압을 걸어 주는 방법과 증착 후 플라즈마 처리를 하는 등의 여러 가지 방법을 사용했다. 전계방출 전류는 1$\times$10-7Torr이사에서 측정하였다. 1회 제작된 용액으로 반복해서 증착한 횟수에 따라 표면의 거치기, 입자의 분포, 전계방출 측정 결과 등의 차이가 관찰되었다. 발광이미지는 전압에 따라 변화하였고, 균일한 발광을 관찰하기 위해서 오랜 시간동안 aging 과정을 거쳐야 했다. 그리고 구 모양의 양극을 사용해서 위치를 변화시키며 시동 전기장을 관찰하여 위치에 따른 전계방출의 차이를 조사하여 발광의 균일성을 알 수 있었다.on microscopy로 분석하였으며 구조 분석은 X-선 회절분석, X-ray photoelectron spectroscopy 그리고Auger electron spectroscope로 하였다. 증착된 산화바나듐 박막의 전기화학적 특성을 분석하기 위하여 리튬 메탈을 anode로 하고 EC:DMC=1:1, 1M LiPF6 액체 전해질을 사용한 Half-Cell를 구성하여 200회 이상의 정전류 충 방전 시험을 행하였다. Half-Cell test 결과 박막의 결정성과 표면상태에 따라 매우 다른 전지 특성을 나타내었다.도상승율을 갖는 경우가 다른 베이킹 시나리오 모델에 비해 효과적이라 생각되며 초대 필요 공급열량은 200kW 정도로 산출되었다. 실질적인 수치를 얻기 위해 보다 고차원 모델로의 해석이 필요하리라 생각된다. 끝으로 장기적인 관점에서 KSTAR 장치의 베이킹 계획도 살펴본다.습파라미터와 더불어, 본 연구에서 새롭게 제시된 주기분할층의 파라미터들이 모형의 학습성과를 높이기 위해 함께 고려된다. 한편, 이러한 학습과정에서 추가적으로 고려해야 할 파라미터 갯수가 증가함에 따라서, 본 모델의 학습성과가 local minimum에 빠지는 문제점이 발생될 수 있다. 즉, 웨이블릿분석과 인공신경망모형을 모두 전역적으로 최적화시켜야 하는 문제가 발생한다. 본 연구에서는 이 문제를 해결하기 위해서, 최근 local minimum의 가능성을 최소화하여 전역적인 학습성과를 높여 주는 인공지능기법으로서 유전자알고리즘기법을 본 연구이 통합모델에 반영하였다. 이에 대한 실증사례 분석결과는 일일 환율예측문제를 적용하였을 경우, 기존의 방법론보다 더 나운 예측성과를 타나내었다.pective" to workflow architectural discussions. The vocabulary suggested

• Journal of Energy Engineering
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• v.21 no.1
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• pp.26-32
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• 2012

This study has been performed Thermal Shock test for analyze the cause of Power drop in PV(Photovoltaic) Module. Thermal Shock test condition was performed with temperature range from $-40^{\circ}C{\sim}85^{\circ}C$. One cycle time is 30min. which are consist of low and high temperature 15min. each other. The test was performed with total 500cycles. EL, I-V were conducted every 100cycle up to 500cycles. Mono Cell resulted in 8% Power drop rates in Bare Cell and 9% in Solar Cell. In the case of Multi Cell resulted in 6% Power drop rates in Bare Cell and 13% in Solar Cell. After Thermal Shock test, Solar Cell's Power drop resulted from surface damages, but in the case of Bare Cell's Power drop had no surface damages. Therefore, Bare Cell's Power drop was confirmed as according to leakage current increase by analysis of Fill Factor after Thermal Shock test. Also, Solar Cell's Power drop rates are higher than that of Bare Cell because of surface damages and consuming electric power increase. From now on, it should be considered that analyzed the reasons of Fill Factor decrease and irregular Power drop in PV module and Cell level using cross section, various conditions and test methods.

• Journal of IKEEE
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• v.22 no.4
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• pp.1025-1030
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• 2018

The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.