• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.1
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• pp.15-22
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• 2008

In this paper, we propose a numerical analysis on reversed current of distributed amplifier based on transmission line theory and proposed a theory to obtain optimum transmission line length to minimize the reversed currents by cancelling those components. The reversed current is analyzed as being simply absorbed into the terminal resistance in the conventional analysis. In the proposed analysis, however, they are designed to be cancelled by each other with opposite phase by the optimal length of the transmission lint Circuit simulation and implementation using pHEMT transistor were performed to validate the proposed theory with the cutoff frequency of 3.6 GHz. From the measurement, maximum gain of 14.5dB and minimum gain of 12.3dB were achieved In the operation band. Moreover, measured efficiency of the proposed distributed amplifier is 25.6% at 3 GHz, which is 7.6%, higher than the conventional distributed amplifier. Measured output power Is about 10.9dBm, achieving 1.7dB higher output power than the conventional one. Those improvement is thought to be based on the cancellation of refersed current.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.90-95
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• 2014

This paper presents a VHF/UHF-band variable gain low noise amplifier for multi-standard mobile TV tuners. A proposed VHF-band variable gain amplifier is composed of a resistive shunt-feedback low noise amplifier to remove external matching components, a single-to-differential amplifier with input PMOS transcoductors to improve low frequency noise performance, a variable shunt-feedback resistor and an attenuator to control variable gain range. A proposed UHF-band variable gain amplifier consists of a narrowband low noise amplifier with capacitive tuning to improve noise performance and interference rejection performance, a single-to-differential with gm gain control and an attenuator to adjust gain control range. The proposed VHF-band and UHF-band variable gain amplifier were designed in a $0.18{\mu}m$ RF CMOS technology and draws 22 mA and 17 mA from a 1.8 V supply voltage, respectively. The designed VHF-band and UHF-band variable gain amplifier show a voltage gain of 27 dB and 27 dB, a noise figure of 1.6-1.7 dB and 1.3-1.7 dB, OIP3 of 13.5 dBm and 16 dBm, respectively.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.101-102
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• 2016

반도체 변압기를 구성하는 단상 계통 연계형 인버터는 역률을 높이기 위해 전류를 계통 전압과 동상으로 제어하는 것이 요구된다. 산업에서 통상적으로 이용되는 비례-적분 제어기는 정현파의 참조 값을 추적할 때 항상 정상 상태 오차를 수반한다. 비례-공진 제어기는 기본 주파수에서 충분히 큰 이득을 도입함으로써 정상 상태 오차를 줄일 수 있다. 그러나 계단 응답에서 정상 상태 오차를 가진다는 단점이 있다. 본 논문에서는 단상 계통 연계형 인버터의 효과적인 전류 제어를 위하여 정현파 추적뿐만 아니라 계단 응답에서 정상 상태 오차 제거가 가능한 제어기를 제안한다. 본 논문에서 제안하는 제어기는 시뮬레이션을 통해 유효성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.295-296
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• 2016

본 논문은 LCL 필터를 사용하는 계통연계형 인버터에 커패시터 전류 피드백 방식의 능동댐핑을 적용한 안정도 향상 방안를 분석하였다. 커패시터 전류 피드백 방식은 커패시터에 저항을 병렬 연결한 수동댐핑과 동일한 특성을 나타내며, 안정도 해석에 $1.5T_s$의 연산 및 PWM 시지연을 고려하였다. 주파수 응답 특성과 이산시간 영역에서 근궤적을 이용하여 안정도를 해석하며, 필터 공진을 저감시키기 위한 능동댐핑의 이득 $k_d$의 범위를 산정하였으며 PSIM 시뮬레이션과 5kW 계통연계형 실험을 통해 필터 공진에 대한 저감 효과를 검증하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.6
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• pp.517-523
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• 2002

A sensorless control of a PM synchronous motor with the compensation of the motor parameter variation is presented. The rotor position is estimated by using the d-axis and q-axis current errors between the real system and motor model of the position estimator. The stator resistance is measured at low speeds when the motor changes its rotating direction and the variation of the stator resistance and back emf constant caused by the temperature variation is compensated. The gains in the position estimator are also adapted according to the motor speeds.

• IE interfaces
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• v.10 no.1
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• pp.95-107
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• 1997

본 논문은 실험계획법을 반도체 공정 및 소자 시뮬레이터에 적용하여, 시뮬레이션 회수를 최소화하고, 동시에 현장과 유사하게 시뮬레이터 내부 파라미터가 튜닝 될 수 있도록 하는 교정 문제에도 활용된 반도체 공정 최적화 사례를 소개한다. 또한, 일반적 시뮬레이터가 실제 현장과의 차이점으로 갖는 문제인 동일한 입력 값에 대해 항상 같은 출력 값이 산출되는 점을 공정의 규격을 고려해 시뮬레이션 함으로써 현장에서의 재현성을 높이고자 하였다. 이는 $0.8{\mu}m$급 BIMOS 공정의 기본 소자 중 하나의 NPN 트랜지스터의 전류이득(Current Gain : hFE) 특성을 최적화하기 위한 주요 공정조건 결정과 연관된 것이며, 기존 방법에 비해 시뮬레이션 횟수를 줄이는 동시에 현장에 직접 투입되는 검증 로트를 최소화시켜 비용과 시간을 절감할 수 있었다. 또한, 얻어진 추전 조건에서 실제 생산된 검증 로트를 통해 시뮬레이션으로부터 얻어진 결과들이 재현됨으로써 제시된 방법의 유용성을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.840-843
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• 2001

In this study, temperature dependency of current gain for AlGaAs/GaAs/GaAs HBT is analytically proposed over the temperature range between 300K and 600K. Energy bandgap, effective mass, intrinsic carrier concentration are considered as temperature dependent parameters. Collector current which is numerically calculated is then analytically expressed to enhance the speed of calculation for current gain. From the results, current gain decreases as the temperature increases. These results will be used to expect the unity current gain frequency f$_{T}$ in conjunction with emitter-base and collector- base capacitances.s.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1135-1137
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• 2001

본 연구는 자계방향 기준 벡터제어 이론에 기초하여 속도 센스리스 벡터제어를 구현한다. 벡터제어는 상태량에 기초한 MRAS (MRAS: Model Reference Adaptive System)방법은 이득정수의 결정이 어려운 결점을 가지고 있다. 여기서는 관측기 이론에 기초하여 2차자속 관측기와 전류센스에서 검출한 전류값으로 속도추정을 행하는 새로운 속도 추정법을 제안한다. 그리고 제안한 방법이 자계 방향 벡터제어 시스템의 실현에 가능성이 있음을 시뮬레이션으로 검토한다.