• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1955-1960
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• 2014

Many routing protocols have been proposed for low-power and ad-hoc networks to deliver command or data among nodes and recently, various researches are carried out about networking scheme considering reliability and scalability. In low-power networking technology, the performance of network layer is closely connected with the operation of data link layer and mesh routing mechanisms based on TDMA MAC are considered for reliability and scalability. This paper proposes mesh routing algorithm utilizing the characteristics of TDMA MAC and topological addressing in TDMA based low-power and ad-hoc networks and implementation results are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.853-855
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• 2009

센서 노드를 위한 운영체제는 제한된 시스템 자원 하에서 동작하므로 전력 소모량을 최소화 시킬 수 있는 시스템 레벨의 저전력 기법과 함께 실시간성을 지원해야 한다. 이에 본 논문에서는 저전력 마이크로프로세서인 ATmega128L 기반의 센서 노드 하드웨어 플랫폼을 설계하고, 센서노드 플랫폼에서 동작하는 멀티스레드 기반의 실시간 운영체제인 RT-UNOS를 개발하였다. 제안한 센서 노드 플랫폼의 동작 검증을 위하여 기존의 센서노드용 운영체제인 TinyOS와 MANTIS, cc-EDF와의 성능을 구현한 센서노드 상에서 실험을 진행하여 비교 분석하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.971-976
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• 2014

In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.555-562
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• 2008

In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.951-954
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• 2003

본 논문에서는 고속. 저전력에 적합한 개방 구조를 갖는 8-비트 500Msmaples/s 2-Step ADC 를 제안하였다. 500Msmaples/s 의 고속 동작을 위해서 기존의 M-DAC을 이용한 폐쇄 구조 대신 개방형 구조를 사용하였다. 이와 더불어 저전력을 구현하기 위해서 analog-latch 를 제안하여 동적 동작을 수행시킴으로써 전력 소모를 줄였으며 , mux 의 구현 시 reset switch를 이용하여 로딩 시간을 개선함으로써 high-speed 에 적합하도록 설계하였다. 제안된 ADC 는 1-poly 6-metal 0.18um CMOS 공정을 이용하였으며 1.8V 전원 전압을 이용하여 250mW 의 전력을 소모하며 500M 샘플링 주파수에서 120MHz 신호 입력 시 7.6 비트의 ENOB를 얻을 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.518-519
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• 2013

신재생 에너지의 용량이 증대하고, 수요가 늘어 남에 따라, 국가 간, 도시 간의 송전이 중요한 이슈로 대두 되고 있으며, 해당 요구 조건을 만족시키기 위해서 초고압 직류 송전 개발이 요구 되고 있다. 이 초고압 직류송전(HVDC)에는 전류형과 전압형으로 나뉘게 되는데, 각 HVDC 에서 사용되는 Valve는 실제 운전 전에 여러 가지 방법으로 검증이 되어야 한다. 합성 시험회로(Synthetic Test Circuit = 이하 STC) 는 전류형 HVDC에서 사용되는 주요 전력변환 장치 인, Thyristor Valve의 동작을 실제 동작 조건에 맞추어 동작을 시켜, 동작의 신뢰성을 검증하는 시험 설비 이다. 기존 STC는 고전압 대전류 회로와 고전압 저전류 회로의 합성 동작으로 Thyristor Valve의 동작을 검증한다. 하지만 제안된 Topology를 이용하면, 고전압 대전류 회로를 저전압 대전류 회로로 사용할 수 있으며, 제작 비용 및 설치 면적 등을 감소 시킬 수 있어 경제적이다.

• Journal of IKEEE
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• v.20 no.3
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• pp.285-290
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• 2016

Inter-symbol interference (ISI) due to channel bandwidth limitation constrains the maximum data rate in high speed I/O. Decision feedback equalizer (DFE) is known as the most popular technique for removing ISI. To ensure fast data transmission, not only removing ISI but also raising maximum operating frequency of the circuit itself by relaxing feedback delay margin is important. For single-ended signaling, DFE should cancel out both ISI and high frequency noises. Low-power operation is as important as fast operation because required DFE elements increase as the data rate goes up. This paper surveys recent techniques for fast DFE by removing ISI and high frequency noises, and low power DFE and discusses about their merits and limitations.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.75-76
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• 2007

이 논문에서는 IS-95와 WCDMA의 Multi-mode로 동작하는 Multi-mode용 저전력 DDC filter 구조를 제안한다. 기존의 DDC구조의 경우 CIC의 통과대역 특성을 향상시켜 주지만, 저지대역의 감쇠특성은 오히려 나빠지는 문제점을 안고 있었다. 제안된 구조는 CIC 데시메이션 필터의 통과대역 특성은 더욱 향상시켜주며, 저지대역의 감쇠특성도 같이 향상시키는 특징을 가진다. 또한 제안된 절터는 각 필터의 면적을 감소시키기 위해 IS-95와 WCDMA의 각각의 모드에 대해 한 개의 필터를 설계한 후 각 모드에 따라 필터 탭 수를 달리하여 동작하는 Multi-mode의 저전력 구조로 구현하였다.