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High Speed Low Power Decision-Feedback Equalizer Techniques

고속 저전력 결정-피드백 이퀄라이저 기술 동향

  • Min, Woong-Ki (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kong, Bai-Sun (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2016.09.06
  • Accepted : 2016.09.27
  • Published : 2016.09.30

Abstract

Inter-symbol interference (ISI) due to channel bandwidth limitation constrains the maximum data rate in high speed I/O. Decision feedback equalizer (DFE) is known as the most popular technique for removing ISI. To ensure fast data transmission, not only removing ISI but also raising maximum operating frequency of the circuit itself by relaxing feedback delay margin is important. For single-ended signaling, DFE should cancel out both ISI and high frequency noises. Low-power operation is as important as fast operation because required DFE elements increase as the data rate goes up. This paper surveys recent techniques for fast DFE by removing ISI and high frequency noises, and low power DFE and discusses about their merits and limitations.

고속 인터페이스에서 채널 대역폭에 의해 생기는 ISI는 최대 데이터 전송속도를 제한한다. ISI를 제거하는 가장 보편적인 기술로 DFE가 있다. 빠른 데이터 송수신을 위해서는 DFE가 효과적으로 ISI를 제거하는 것도 중요하지만 피드백 지연 등을 완화시켜 회로 자체의 최대 동작 주파수도 증가시켜야 한다. 또한, 싱글 엔디드 시그널링에서는 DFE가 ISI뿐만이 아닌 고주파 잡음도 효과적으로 제거하여야 한다. 한편, 데이터 전송 속도가 올라감에 따라 늘어 나는 ISI 및 고주파 잡음을 제거하기위한 DFE 구성품의 수가 증가한다. 이는 곧 추가의 전력소모를 야기하므로 고속 동작뿐만 아니라 저전력 동작도 주목할 필요가 있다. 본 논문에서는 ISI와 고주파 잡음을 효과적으로 제거하는 고속 DFE 및 저전력으로 동작하는 DFE의 동작 방식과 이들이 갖고 있는 장단점을 소개한다.

Keywords

References

  1. J. H. Lee, "Low - C ost CRCS cheme by Using DBI(Data Bus In version) for High Speed Semiconductor Memory ," j.inst.Korean.electr.electron.eng, vol.14, no.2, pp. 33-40, Mar. 2010.
  2. H. -J. Chi, J. -S. Lee, S. -H. Jeon, S. -J. Bae, Y. -S. Sohn, J. -Y. Sim, and H. -J. Park, "A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface," IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2053-2063, Sep. 2011. https://doi.org/10.1109/JSSC.2011.2136590
  3. S. -J. Bae, H. -J. Chi, J. -S. Lee, J. -Y. Sim, and H. -J. Park, "A 2Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single Ended Signaling," IEEE J. Solid-State Circuits, vol. 56, no. 8, pp. 1645-1656, Aug. 2009.
  4. T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, "A 12Gb/s 11mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1298-1305, Apr. 2009. https://doi.org/10.1109/JSSC.2009.2014733
  5. K. Jung, A. Amirkhany, and K. Kaviani, "A 0.94mW/Gb/s 22Gb/s 2-Tap Partial -Response DFE Receiver in 40nm LP CMOS," ISSCC Dig. Tech. Papers, 2013.
  6. H. -W. Lim, S. -W. Choi, S. -K. Lee, C. -H. Baek, J. -Y. Lee, G. -C. Hwang, B. -S. Kong, and Y. -H. Jun, "A 5.8Gb/s Adaptive Integrating Duobinary-Based DFE Receiver for Multi-Drop Memory Interface," ISSCC Dig. Tech. Papers, 2015.
  7. M. H. Nazari, and A. E. Neyestanak, "A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation," IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2420-2432, Oct. 2012. https://doi.org/10.1109/JSSC.2012.2203870
  8. A. Agrawal, J. F. Bulzacchelli, T. O. Dickson, Y. Liu, J. A. Tierno, and D. J. Friedman, "A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS," IEEE J. Solid-State Circuits, vol. 47, no. 12, pp. 3220-3231, Dec. 2012. https://doi.org/10.1109/JSSC.2012.2216412
  9. K. J. Wong, A. Rylyakov, and C. K. Yang, "A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 881-888, Apr. 2007. https://doi.org/10.1109/JSSC.2007.892189
  10. W. H. Shin, Y. H. Jun, and B. S. Kong, "A DFE Receiver with Equalized VREF for Multidrop Single-Ended Signaling," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 7, pp. 412-416, Jul. 2013. https://doi.org/10.1109/TCSII.2013.2258271
  11. S. Shahramian, H. Yasotharan, and A. C. Carusone, "Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 6, pp. 326-330, Jun. 2012. https://doi.org/10.1109/TCSII.2012.2195055
  12. S. Shahramian, and A. C. Carusone, "A 0.41pJ/Bit 10Gb/s Hybrid 2 IIR and 1 Discrete Time DFE Tap in 28nm LP CMOS," IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722-1735, Jul. 2015. https://doi.org/10.1109/JSSC.2015.2402218
  13. S. M. Lee, J. H. Kim, J. Kim, Y. Kim, H. Lee, J. Y. Sim, and H. J. Park, "A 27% Reduction in transceiver Power for Single Ended Point to Point DRAM Interface with the Termination Resistance of $4{\times}Z_0$ at both TX and RX," ISSCC Dig. Tech. Papers, 2013.