• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.2
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• pp.25-34
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• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.