• KSCE Journal of Civil and Environmental Engineering Research
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• v.14 no.1
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• pp.119-129
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• 1994

This paper describes a $C^{{+}{+}}$ free vibration analysis program of structures for personal computer. This program was developed by object oriented programming method which is the latest trend in programming practice. The object-oriented programming method which has the superior reuseability and expansibility to procedural programming provides various choice of menus and easy modification of the program, and reduces the development time and size of the program. This object-oriented free vibration analysis program written in $C^{{+}{+}}$ language consists of Vector and Matrix classes, Structural Analysis and GUI classes. The efficiency and validity of the program were examined by solving several numerical examples. The static and free vibration analyses of the framed structures were satisfactorily performed by this program on a personal computer.

• Journal of the Korea Society of Computer and Information
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• v.25 no.9
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• pp.81-90
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• 2020

In order to operate multi drone efficiently, existing control methods must be improved, and drones must be able to construct communication networks autonomously. FANET(Flying Ad-Hoc Network), which is being considered as an alternative to solving these problems, is based on ad hoc network technology and can be exposed to a variety of security vulnerabilities. However, due to the limited computational power and memory of FANET nodes, and rapid and frequent changes in network topology, it is not easy to apply the existing security measures to FANET without modification. Thus, this paper proposes lightweight security measures applicable to FANET, which have distinct characteristics from existing ad hoc networks by utilizing PUF technology. The proposed security measures utilize unique values generated by non-replicable PUFs to increase the safety of AODV, FANET's reactive routing protocol, and are resistant to various attacks.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.3
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• pp.385-396
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• 1999

In the process of structural design for large-scale structures with several thousands of degrees of freedom, a plethora of structural calculations with large amount of data storage are required to obtain the forces and displacements of the members. However, current computational environment with single microprocessor such as a personal computer or a workstation is not capable of generating a high-level of efficiency in structural analysis and design process for large-scale structures. In this paper, a high-performance parallel computing system interconnected by a network of personal computers is proposed for an efficient structural analysis. Two distributed structural analysis algorithms are developed in the form of distributed or parallel preconditioned conjugate gradient (DPCG) method. To enhance the performance of the developed distributed structural analysis algorithms, the number of communications and the size of data to be communicated are minimized. These algorithms are applied to the structural analyses of three large space structures as well as a 144-story tube-in-tube framed structure.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.359-364
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• 2014

In this paper, we propose a method for extracting a road area by using the mean-shift method and connected-component method. Mean-shift method is very effective to divide the color image by the method of non-parametric statistics to find the center mode. Generally, the feature points of road are extracted by using the information located in the middle and bottom of the road image. And it is possible to extract a road region by using this feature-point and the partitioned color image. However, if a road region is extracted with only the color information and the position information of a road image, it is possible to detect not only noise but also off-road regions. This paper proposes the method to determine the road region by eliminating the noise with the closing / opening operation of the morphology, and by extracting only the portion of the largest area using a connected-components method. The proposed method is simulated and verified by applying the captured road images.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.71-78
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• 2005

A K-Best algerian is known as optimal for implementing the maximum-likelihood detector (MLD), since it has a fixed maximum complexity compared with the sphere decoding or the maximum-likelihood decoding algorithm. However the computational complexity of the K-Best algrithm is still prohibitively high for practical applications when K is large enough. If small value of K is used, the maximum complexity decreases but error flooring at high SNR is caused by error propagation. In this paper, a K-reduction scheme, which reduces K according to each search level, is proposed to solve error propagation problems. Simulations showed that the proposed scheme provides the improved performance in the bit error rate and also reduces the average complexity compared with the conventional scheme.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• The Journal of the Korea Contents Association
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• v.16 no.8
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• pp.706-716
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• 2016

Because of efficient space utilization and fast key search times, B-trees have been widely accepted for the use of indexes in HDD-based DBMSs. However, when the B-ree is stored in flash memory, its costly operations of node updates may impair the performance of a DBMS. This is because the random updates in B-tree's leaf nodes could tremendously enlarge I/O costs for the garbage collecting actions of flash storage. To solve the problem, we make all the parents of leaf nodes the virtual nodes, which are not stored physically. Rather than, those nodes are dynamically generated and buffered by referring to their child nodes, at their access times during key searching. By performing node updates and tree reconstruction within a single flash block, our proposed B-tree can reduce the I/O costs for garbage collection and update operations in flash. Moreover, our scheme provides the better performance of key searches, compared with earlier flash-based B-trees. Through a mathematical performance model, we verify the performance advantages of the proposed flash B-tree.

• Journal of Korea Multimedia Society
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• v.12 no.7
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• pp.922-928
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• 2009

In H.264 as the newest video standard, 9 modes are used in order to predict the signal values of a block composed with several pixels by intra prediction. From these process, H.264 can bring high compression ratio in the encoded signal but the use of total 9 modes can give the inefficiency of the increase of the complexity induced by the amount of operation processing or the number of searching which is applied to compare adjacent pixels. This paper proposes a simplification method of prediction mode for the intra-picture coding by considering subjective interest region. There are certain region being interested within a picture of the video sequence. This region requires better subjective picture quality than the other regions. The proposed method increases the simplification of prediction mode by providing just essential modes of total 9 modes for less interest regions compared with the interest region. It is possible to get the additional 11%$\sim$15% simplification of the prediction mode by the proposed method, compared with the conventional method which simplifies the prediction mode for all of the picture by using the prediction characteristics only.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.28-35
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• 2006

This paper presents a new 3.3-1 V synchronous buck DC/DC converter that employs CMOS operational transconductance amplifiers (OTAs) as circuit-building blocks. An error amplifier OTA in a PWM circuit is compensated for to improve temperature stability. The temperature coefficient of the transconductance gain of the compensated OTA is less than $150\;ppm/^{\circ}C\;over\;0-100^{\circ}C$. The HSPICE simulation results of the $0.3{\mu}m$ standard CMOS technology show that the efficiency of the proposed converter is as high as 80% in the load current range of 40-125 mA. These results show that the proposed converter is adequate for use in battery-operated systems.