Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
권호 표지
DOI QR코드

DOI QR Code

An Efficient Multiplexer-based AB2 Multiplier Using Redundant Basis over Finite Fields

  • Kim, Keewon (Dept. of Applied Computer Engineering, Dankook University)
  • Received : 2019.11.20
  • Accepted : 2020.01.07
  • Published : 2020.01.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, we propose a multiplexer based scheme that performs modular AB2 multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB2 multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB2 multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB2 multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

본 논문에서는 유한체상의 여분 기저(redundant basis)를 사용한 모듈러 AB2 곱셈을 수행하는 멀티플렉서(multiplexer) 기반의 기법을 제안한다. 그리고 제안한 기법을 사용하여 효율적인 멀티플렉서 기반의 세미-시스톨릭(semi-systolic) AB2 곱셈기를 제안한다. 모듈러 AB2 곱셈기의 셀 내부의 연산을 멀티플렉서로 처리할 수 있는 수식을 유도한다. 멀티플렉서를 이용하여 셀을 구현하여, 셀의 지연시간을 감소시킨다. 기존의 구조들과 비교하면, 제안한 AB2 곱셈기는 Liu 등, Lee 등, Ting 등, 및 Kim-Kim의 곱셈기들의 AT 복잡도보다 약 80.9%, 61.8%, 61.8%, 및 9.5% 가량이 감소되었다. 따라서, 제안한 곱셈기는 VLSI(very large scale integration) 구현에 적합하며 다양한 응용에 쉽게 적용할 수 있다.

Keywords

References

  1. A. J. Menezes, P.C. van Oorschot, S.A. Vanstone, "Handbook of Applied Cryptography" Boca Raton, FL, CRC Press, 1996.
  2. R. E. Blahut, "Theory and Practice of Error Control Codes" Reading, MA, Addison-Wesley, 1983.
  3. N. Kobliz, “Elliptic Curve Cryptography,” Math. Computation, Vol. 48, No. 177, pp. 203-209, Jan. 1987. DOI: 10.1090/S0025-5718-1987-0866109-5
  4. P. Montgomery, “Modular Multiplication without Trial Division,” Mathematics of Computation, Vol. 44, No. 170, pp. 519-521, Apr. 1985. DOI: 10.1090/S0025-5718-1985-0777282-X
  5. C. K. Koc, T. Acar, “Montgomery Multiplication in GF(2k),” Designs Codes and Cryptography, Vol. 14, No. 1, pp. 57-69, Apr. 1998. DOI: 10.1023/A:1008208521515
  6. C. Y. Lee, J. S. Horng, I. C. Jou, "Low-complexity Bit-parallel Systolic Montgomery Multipliers for Special Classes of GF(2m)," IEEE Transactions on Computers, Vol. 54, No. 9, pp. 1061-1070, July 2005. DOI: 10.1109/TC.2005.147
  7. C. W. Chiou, C. Y. Lee, A. W. Deng, J. M. Lin, “Concurrent Error Detection in Montgomery Multiplication over GF(2m),” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 2, pp. 566-574, Feb. 2006. DOI: 10.1093/ietfec/e89-a.2.566
  8. A. Hariri, A. Reyhani-Masoleh, "Bit-serial and Bit-parallel Montgomery Multiplication and Squaring over GF(2m)," IEEE Transactions on Computers, Vol. 58, No. 10, pp. 1332-45, May 2009. DOI: 10.1109/TC.2009.70
  9. A. Hariri, A. Reyhani-Masoleh, "Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields," IEEE Transactions on Computers, Vol. 60, No. 9, pp. 1341-53, Sep. 2011. DOI: 10.1109/TC.2010.258
  10. K. W. Kim, W. J. Lee, “Efficient Cellular Automata Based Montgomery AB2 Multipliers over GF(2m),” IETE Technical Review, Vol. 31, No. 1, pp. 92-102, Jan. 2014. DOI: 10.1080/02564602.2014.891383
  11. K. W. Kim, J. C. Jeon, “Polynomial Basis Multiplier Using Cellular Systolic Architecture,” IETE Journal of Research, Vol. 60, No. 2, pp. 194-199, Jun. 2014. DOI: 10.1080/03772063.2014.914699
  12. S. H. Choi, K. J. Lee, "Low Complexity Semi-systolic Multiplication Architecture over GF(2m)," IEICE Electron. Express, Vol. 11, No. 20, pp. 20140713, Oct. 2014. DOI: 10.1587/elex.11.20140713
  13. K. W. Kim, J. C. Jeon, "A Semi-systolic Montgomery Multiplier over GF(2m)," IEICE Electonics Express, Vol. 12, No. 21, pp. 20150769, Nov. 2015. DOI: 10.1587/elex.12.20150769
  14. S. W. Wei, “A Systolic Power-sum Circuit for GF(2m),” IEEE Transactions on Computers, Vol. 43, No. 2, pp. 226-229, Feb. 1994. DOI: 10.1109/12.262128
  15. C. L. Wang, J. H. Guo, "New Systolic Arrays for C+AB2, Inversion, and Division in GF(2m)," IEEE Transactions on Computers, Vol. 49, No. 10, pp. 1120-1125, Oct. 2000. DOI: 10.1109/12.888047
  16. C. H. Liu, N. F. Huang, C. Y. Lee, “Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-complexity Cellular Architecture,” IEICE Transactions on Fundamentals of Electronics, Vol. E83-A, No. 12, pp. 2657-2663, Dec. 2000.
  17. C. Y. Lee, E. H. Lu, L. F. Sun, “Low-complexity Bit-parallel Systolic Architecture For Computing AB2+C in a Class of Finite Field GF(2m),” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 5, pp. 519-523, May 2001. DOI: 10.1109/82.938363
  18. Y. R. Ting, E. H. Lu, J. Y. Lee, “Low Complexity Bit-parallel Systolic Architecture for Computing C+AB2 Over A Class of GF(2m),” Integration, the VLSI journal, Vol. 37, No. 3, pp. 167-176, Aug. 2004. DOI: 10.1016/j.vlsi.2004.01.003
  19. C. Y. Lee, A. W. Chiou, J. M. Lin, “Low-complexity Bit-parallel Systolic Architectures for Computing A(x)B2(x) over GF(2m),” IEEE Proceedings of Circuits Devices and Systtems, Vol. 153, No. 4, pp. 399-406, Aug. 2006. DOI: 10.1049/ip-cds:20050188
  20. K. W. Kim, W. J. Lee, “Low-complexity Parallel and Serial Systolic Architectures for AB2 Multiplication in GF(2m),” IETE Technical Review, Vol. 30, No. 2, pp. 134-141, 2013. DOI: 10.4103/0256-4602.110552
  21. K. W. Kim, W. J. Lee, "An Efficient Parallel Systolic Array for AB2 over GF(2m)," IEICE Electronics Express, Vol. 10, No. 20, pp. 20130585, 2013. DOI: 10.1587/elex.10.20130585
  22. T. W. Kim, K. W. Kim, "Low-latency Montgomery AB2 Multiplier Using Redundant Representation over GF(2m)," IEMEK Journal of Embedded Systems and Applications, Vol. 12, No. 1, Feb. 2017. DOI: 10.14372/IEMEK.2017.12.1.11
  23. K. Z. Pekmestzi, "Multiplexer-based Array Multipliers," IEEE Trans. Comput., Vol. 48, No. 1, pp.15-23, Jan. 1999. DOI: 10.1109/12.743408
  24. H. W. Chang, W. Y. Liang, C. W. Chiou, "Low Cost Dual-Basis Multiplier over GF(2m) Using Multiplexer Approach," Knowledge Discovery and Data Mining. Advances in Intelligent and Soft Computing, Vol 135. pp. 185-192, 2012. DOI: 10.1007/978-3-642-27708-5_25
  25. S. S. Priya, K. G. Das, N. M. SivaMangai, P. K. Kumar, "Multiplexer Based High Throughput S-box for AES Application," 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, pp. 242-247, Feb. 2015, DOI: 10.1109/ECS.2015.7124901
  26. G. Drolet, “A New Representation of Elements of Finite Fields Yielding Small Complexity Arithmetic Circuits,” IEEE Transactions on Computers, Vol. 47, No. 9, pp. 938-946, Sep. 1998. DOI: 10.1109/12.713313
  27. H. Wu, M. A. Hasan, I. F. Blake, S. Gao, "Finite Field Multiplier Using Redundant Representation," IEEE Transactions on Computers, Vol. 51, No. 11, pp. 1306-1316, Nov. 2002. DOI: 10.1109/TC.2002.1047755
  28. R. J. Baker, H. W. Li, D. E. Boyce, "CMOS Circuit, Design, Layout, and Simulation" New York, IEEE Press, 1998.
  29. STMicroelectronics. http://www.st.com.