• Title/Summary/Keyword: 암호/복호화

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A Study of DES(Data Encryption Standard) Property, Diagnosis and How to Apply Enhanced Symmetric Key Encryption Algorithm (DES(Data Encryption Standard) 속성 진단과 강화된 대칭키 암호 알고리즘 적용방법)

  • Noh, Si Choon
    • Convergence Security Journal
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    • v.12 no.4
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    • pp.85-90
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    • 2012
  • DES is a 64-bit binary, and each block is divided into units of time are encrypted through an encryption algorithm. The same key as the symmetric algorithm for encryption and decryption algorithms are used. Conversely, when decryption keys, and some differences may apply. The key length of 64 bits are represented by two ten thousand an d two 56-bit is actually being used as the key remaining 8 bits are used as parity check bits. The 64-bit block and 56-bit encryption key that is based on a total of 16 times 16 modifier and spread through the chaos is completed. DES algorithm was chosen on the strength of the password is questionable because the most widely available commercially, but has been used. In addition to the basic DES algorithm adopted in the future in the field by a considerable period are expected to continue to take advantage of the DES algorithm effectively measures are expected to be in the field note.

A Security Hole in Comparable Encryption (비교가능 암호화의 허점)

  • Kim, Sangjin;Oh, Heekuck
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.23 no.2
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    • pp.267-271
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    • 2013
  • Comparable encryption allows a verifier to test whether given two ciphertexts from a probabilistic public key cryptosystem are encryption of the same message without decrypting them. Recently, Yang et al. proposed such scheme and Lee et al. and Tang independently modified Yang et al.'s system to restrict the entity who can perform the verification. However, the original Yang et al.'s scheme has a flaw that enables two ciphertexts which are not encryption of the same message to pass the test. In this paper, we concretely show the faults in all three schemes considered and analyze the effect of this flaw in the use of such schemes in applications.

Improvement of Okamoto-Uchiyama Probabilistic Public Key Cryptosystem (Okamoto-Uchiyama 확률 공개키 암호 방식의 효율성 개선)

  • Choi, Duk-Hwan;Kim, Hyun-Jue;Choi, Seung-Bok;Won, Dong-Ho
    • Journal of KIISE:Information Networking
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    • v.29 no.4
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    • pp.346-351
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    • 2002
  • We improve a new probabilistic public key cryptosystem, in which the one wav function was defined only on the discrete logarithmic functions, proposed by Okamoto and Uchiyama. The plaintexts are calculated from the modular product of two these functions, one of which has a fixed value depending on a given public key. The improvement is achieved by a well-chosen public key assuming an unit element 1 as the fixed function value. Because it is possible to reduce the number of operations at the decryption. Also the concrete method for a public key of our improved scheme is suggested.

Security Analysis on the Full-Round SCO-1 (블록 암호 SCO-1에 대한 안전성 분석)

  • Jeong, Ki-Tae;Lee, Chang-Hoon;Kim, Jong-Sung;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.18 no.4
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    • pp.27-35
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    • 2008
  • In this paper we show that the full-round SCO-1[12] is vulnerable to the related-key differential attack. The attack on the full-round SCO-1 requires $2^{61}$ related-key chosen ciphertexts and $2^{120.59}$ full-round SCO-1 decryptions. This work is the first known attack on SCO-1.

FPGA-Based Post-Quantum Cryptography Hardware Accelerator Design using High Level Synthesis (HLS 를 이용한 FPGA 기반 양자내성암호 하드웨어 가속기 설계)

  • Haesung Jung;Hanyoung Lee;Hanho Lee
    • Transactions on Semiconductor Engineering
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    • v.1 no.1
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    • pp.1-8
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    • 2023
  • This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

An Implementation of Authentication and Encryption of Multimedia Conference using H.235 Protocol (H.235 프로토콜에 의한 영상회의의 인증과 암호화 구현)

  • Sim, Gyu-Bok;Lee, Keon-Bae;Seong, Dong-Su
    • The KIPS Transactions:PartC
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    • v.9C no.3
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    • pp.343-350
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    • 2002
  • This paper describes the implementation of H.235 protocol for authentication and media stream encryption of multimedia conference systems. H.235 protocol is recommended by ITU-T for H.323 multimedia conference security protocol to prevent from being eavesdropped and modified by an illegal attacker. The implementation in this paper has used password-based with symmetric encryption authentication. Media streams are encrypted using the Diffie-Hellman key exchange algorithm and symmetric encryption algorithms such as RC2, DES and Triple-DES. Also, 128-bit Advanced Encryption Standard and 128-bit Korean standard SEED algorithms are implemented for the future extension. The implemented authentication and media stream encryption has shown that it is possible to identify terminal users without exposing personal information on networks and to preserve security of multimedia conference. Also, encryption delay time and used memory are not increased even though supporting media stream encryption/decryption, thus the performance of multimedia conference system has not deteriorated.

Efficient Multi-Bit Encryption Scheme Using LWE and LWR (LWE와 LWR을 이용한 효율적인 다중 비트 암호화 기법)

  • Jang, Cho Rong;Seo, Minhye;Park, Jong Hwan
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.28 no.6
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    • pp.1329-1342
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    • 2018
  • Recent advances in quantum computer development have raised the issue of the security of RSA and elliptic curve cryptography, which are widely used. In response, the National Institute of Standards and Technology(NIST) is working on the standardization of public key cryptosystem which is secure in the quantum computing environment. Lattice-based cryptography is a typical post-quantum cryptography(PQC), and various lattice-based cryptographic schemes have been proposed for NIST's PQC standardization contest. Among them, EMBLEM proposed a new multi-bit encryption method which is more intuitive and efficient for encryption and decryption phases than the existing LWE-based encryption schemes. In this paper, we propose a multi-bit encryption scheme with improved efficiency using LWR assumption. In addition, we prove the security of our schemes and analyze the efficiency by comparing with EMBLEM and R.EMBLEM.

A High-speed Masking Method to protect ARIA against Side Channel Analysis (부채널 분석에 안전한 고속 ARIA 마스킹 기법)

  • Kim, Hee-Seok;Kim, Tae-Hyun;Ryoo, Jeong-Choon;Han, Dong-Guk;Hong, Seok-Hie
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.18 no.3
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    • pp.69-77
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    • 2008
  • In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption, and key-schedule) are well-known. Applications of masking methods are able to vary in different block ciphers, therefore suitable masking methods about each ciphers have been researched. Existed methods of ARIA have many revisions of mask value. And because existed masking methods pay no regard for key schedule, secret information can be exposed. In the case of ARIA, this problem is more serious than different block ciphers. Therefore we proposes an efficient masking scheme of ARIA including the key-schedule. Our method reduces time-complexity of ARIA encryption, and solve table-size problem of the general ARIA masking scheme from 256*8 byte to 256*6 byte.

Efficient and Secure User Authentication and SDP Encryption Method in SIP (일회성 암호를 이용한 효율적이고 안전한 SIP 사용자 인증 및 SDP 암호화 기법)

  • Kim, Jung-Je;Chung, Man-Hyun;Cho, Jae-Ik;Shon, Tae-Shik;Moon, Jong-Sub
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.22 no.3
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    • pp.463-472
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    • 2012
  • This paper propose a security method that performs mutual authentication between the SIP UA and the server, check for integrity of the signaling channel and protection of SDP information for VoIP using a One-Time Password. To solve the vulnerability of existing HTTP Digest authentication scheme in SIP, Various SIP Authentication schemes have been proposed. But, these schemes can't meet security requirements of SIP or require expensive cryptographic operations. Proposed method uses OTP that only uses hash function and is updated each authentication. So Proposed method do not require expensive cryptographic operations but performs user authentication efficiently and safely than existing methods. In addition, Proposed method verifies the integrity of the SIP messages and performs SDP encryption/decryption through OTP that used for user authentication. So Proposed method can reduce communication overhead when applying S/MIME or TLS.

A Public-key Cryptography Processor supporting P-224 ECC and 2048-bit RSA (P-224 ECC와 2048-비트 RSA를 지원하는 공개키 암호 프로세서)

  • Sung, Byung-Yoon;Lee, Sang-Hyun;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.22 no.3
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    • pp.522-531
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    • 2018
  • A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.