• Journal of IKEEE
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• v.13 no.1
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• pp.77-86
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• 2009

A wavelet Electrocardiogram(ECG) detector and its analog-to-digital converter(ADC) for low-power implantable cardiac pacemakers are presented in this paper. The proposed wavelet-based ECG detector consists of a wavelet decomposer with wavelet filter banks, a QRS complex detector of hypothesis testing with wavelet-demodulated ECG signals, and a noise detector with zero-crossing points. To achieve high-detection performance with low-power consumption, the multi-scaled product algorithm and soft-threshold algorithm are efficiently exploited. To further reduce the power dissipation, a low-power ADC, which is based on a Successive Approximation Register(SAR) architecture with an on/off-time controlled comparator and passive sample and hold, is also presented. Our algorithmic and architectural level approaches are implemented and fabricated in standard $0.35{\mu}m$ CMOS technology. The testchip shows a good detection accuracy of 99.32% and very low-power consumption of $19.02{\mu}W$ with 3-V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1753-1758
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• 2012

This paper introduces analog FIR filters based on a distributed amplifier and analyzes the proposed filter's characteristics. A simple design method of an analog FIR filter based on the digital filter design technique is also introduced. The proposed analog FIR filters are a moving average(MA) and a comb type filters with no multiplier. This simple structures of the proposed filters may enable to operate at multi-GHz frequency range and applicable to combine a filter and an amplifier of RF system. The proposed analog FIR filters were implemented with standard $0.18{\mu}m$ CMOS technology. The designed GHz analog FIR filters are simulated by Cadence Spectre and compared to the results of digital FIR filters obtained from MATLAB simulations. From the simulation results, the characteristics of the proposed analog FIR filters are fairly well matched with those of digital FIR filters.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.369-372
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• 2005

산업체에서 사용되는 BLDC 모터 제어보드의 경우에는 대량 생산을 통하여 제작하며, 제작과정에서 발생한 불량 제어보드는 모터의 초기 기동실패와 고속회전시의 소음 및 화재 발생 등의 원인일뿐만이 아니라 이를 사용하여 응용제품을 생산하는 업체의 품질관리면에서 제어보드의 이상유무 확인이 반드시 필요하다. 일반적인 모터 제어보드의 이상 유무는 육안 및 소음에 의한 방법으로 모토의 기동실패나 고속 회전을 통한 소음등으로부터 경험에 의해 판단한다. 그러나 고속 회전시 발생되는 소음으로 모터 제어보드의 이상유무를 판단하게 되면 이상유무 판단에 필요한 시간이 길어져 대규모 생산과정에 적합하지 않을 뿐만아니라 작업자의 경험에 의존하게 됨으로써 생산성에 지장을 주게된다. 또한 검사시간을 줄이기 위하여, 저속 회전만으로 이상유무를 판단하고자 할 경우 소음정도가 약해 이상유무를 판단하기가 매우 어렵고 더욱더 숙련된 검사자를 필요로 하게 되므로 생산공정에 자동검사기의 도입이 필요하디. 본 논문은 BLDC 모터 제어기의 이상이 발생할 수 있는 경우를 고찰하고, 이러한 BLDC 모터 제어보드의 이상상태가 납땜불량 및 소자 파괴 의하여 입${\cdot}$출력이 비정상적으로 이루어 질 경우의 전류신호와 정상일 때의 전류신호를 비교분석한 후 이를 검출할 수 있는 아날로그 회로를 구현하고 실험을 통하여 검증을 하였다. 또한 이러한 BLDC모터 제어기의 검사기를 아날로그 회로로 구현할 경우의 주의점을 고찰한다.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.384-387
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• 2010

지상파 방송이 아날로그에서 디지털 방송으로 전환됨에 따라 아날로그 TV 방송신호와 디지털 TV(DTV) 방송신호간의 생성과 복조방식이 상이함에 따라 전파환경에 의한 방송품질의 변화가 예상된다. 따라서 DTV 방송신호의 수신을 위한 전파 음영지역 해소가 품질 확보에 필수적인 관심사로 대두되고 있으며, 이에 대한 대책으로 타당성 및 신뢰성 있는 전계강도 예측 방법에 근거하여 적정지역의 송신소 및 중계기 설치가 전파 품질 개선에 크게 기여할 것으로 여겨진다. 본 논문에서는 국제적으로 30 MHz ~ 3000 MHz 대역 지상파 방송서비스의 전파특성 예측에 활발히 이용되는 ITU-R 권고 P.1546 전파모델을 이용하여 점-대-지역 전계강도 예측을 위한 계산 방법을 제시하고, 수치 계산 결과를 비교 및 분석한다. 제시된 방법은 DTV 수신지역의 전계강도 예측을 통한 신호의 품질 분석은 물론, 양호한 전파환경 구축에 필요한 중계기 위치설정, 인접대역에 의한 간섭 및 양립성 분석 등에 직접 활용이 가능하다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.448-451
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• 2011

SoC에서 칩 내부의 온도를 측정하기 위한 proportional-to-absolute-temperature (PTAT) 회로와 sensing 된 아날로그 신호를 디지털로 변환하기 위해 4-bit analog-to-digital converter (ADC)로 구성된 temperature sensor를 제안한다. CMOS 공정에서 vertical PNP 구조를 이용하여 PTAT 회로가 설계되었다. 온도변화에 둔감한 ADC를 구현하기 위해 아날로그 회로를 최소로 사용하는 successive approximation (SA) ADC가 이용되었다. 4-bit SA ADC는 capacitor DAC와 time-domain 비교기를 이용함으로 전력소모를 최소화하였다. 제안된 temperature sensor는 2.5V $0.25{\mu}m$ 1-poly 9-metal CMOS 공정을 이용하여 설계되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. Temperature sensor의 면적과 전력 소모는 각각 $130{\times}390\;um^2$과 868 uW이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1985-1992
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• 2011

PE(Passive Entry) is an automotive technology which allows a driver to lock and unlock door of vehicle without using smart key buttons personally. PG(Pssive Go) is an automotive technology which offers the ability to start and stop the engine when there is a driver in vehicle with smart key. When these two functions are unified, we call it PEG(Passive Entry/Go). LF(Low Frequency) antenna driver which is one of core technologies in PEG is composed of a digital part which processes commands and an analog part which generates sine waveform. The digital part of antenna driver receives commands from MCU(or ECU), and processes requested commands by MCU, and stores antenna-related driver commands and data on an internal FIFO block. The digital part takes corresponding actions for commands read from FIFO and then transfers modulated LF data to analog part. The analog part generates sine waveform and transmits outside through antenna. The designed digital part for LF antenna driver can acomplish faster LF data transmission than that of conventional product. LF antenna driver can be applicable to the areas such as PEG for automotive and gate opening and closing of building.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.