• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1A
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• pp.10-15
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• 2010

This paper proposes a practical method for AGC (Automatic Gain Control) in WiBro (Wireless Broadband) AT (Access Terminal) system. Downlink packets in this system consist of preamble symbols for AGC, AFC (Automatic Frequency Control) and other purposes and data symbols for traffic transmission. In this paper we compare theoretical BER (Bit Error Rate) performance with simulation results and produce optimum parameters for AGC in this system. And we propose an efficient AGC scheme before synchronization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.689-692
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• 2008

WAVE based on OFDM is made for vehicle to vehicle wireless communication. Its performance is decreased by continual timing delay in multipath fading channels after starting initial timing synchronization. In this paper, the tracking algorithm that synchronizes symbol timing is proposed to continually compensate additional timing delay. Computer simulation of the proposed algorithm is performed in the worst communication environment that applies to maximum timing delay. Computer simulation shows that the proposed algorithm can improve the system performance in various channel conditions.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.53-58
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• 2007

OFDM (orthogonal frequency division multiplexing) is an effective modulation technique for high speed transmission over fading channels. However, it has a high bit error rate in the receiver if there is an error on frame synchronization because of phase rotation. A coherent OFDM system has to acquire exact timing synchronization of fraction and integer sampling positions. When a sampling offset exist the performance of a receiver will be degraded severely. In this paper, we propose an algorithm that acquires the fractional sampling offset in OFDM systems. This scheme compares the channel impulse responses with the early and late sampled signals having 0.5 sample offset from the estimated sampling positions by correlation with the received and training samples. Its performance is verified by computer simulations in multipath channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1436-1444
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• 2000

In this paper, we propose the joint carrier and symbol timing recovery algorithm using repetitive preamble and differential detection for burst modem. The proposed algorithm can estimate the frequency offset and the symbol timing error regardless of the amount of frequency offset, with a high accuracy, even using very short preamble and at low SNR values. The algorithms for continuous phase frequency shift keying (CPFSK) and phase shift keying (PSK) types are developed. Through computer simulations, we compare the proposed algorithm with the existing algorithms on the estimation accuracy in terms of the preamble length, and analyze those bit error rate(BER) performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3A
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• pp.205-212
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• 2009

A novel channel estimation scheme is proposed for coherent Impulse Radio Ultra Wideband (IR-UWB) system based on IEEE 802.15.4a specification. By extracting and utilizing the information on the frequency synchronization, the proposed channel estimation algorithm improves the receiver performance even under the restricted number of preamble symbols in IEEE 802.15.4a signal format. Simulation results over the IEEE 802.15.4a channel models show the performance gain with the proposed algorithm compared to ordinary channel estimation method.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.83-91
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• 2003

High-speed QPSK demodulator has been in important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes all-digital QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. All-digital QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tacking to fabricate FPGA chip. The testing results of the implemented onto CPLD-EPF10K100GC 503-4 chip show demodulation speed is reached up to 2.6[Mbps]. If it is implemented a CPLD chip with speed grade 1, the demodulation speed can be faster by about 5 times. Actually in case of designing by ASIC, its speed my be faster than CPLD by 5 times. Therefore, it is possible to fabricate the all-digital QPSK demodulator chipset with speed of 50[Mbps].

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.10a
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• pp.17-22
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• 1990

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.109-114
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• 2015

Frame synchronization is achieved by correlation between received symbols and a preamble pattern which is periodically appended at a frame header. In this paper, we deal with a frame detection method complaint with satellite-based DVB-S2 system. In DVB-S2, frame synchronization is performed under the low signal-to-noise ratio(SNR), a large frequency offset which can be up to 20% of a symbol transmission rate and unknown modulation schemes ranging from QPSK to 32-APSK. In this environment, we propose a method combining differential correlation based on SOF and PLSC with an accumulated correlation method for the detection of frame structures. In addition, detection performances about mean acquisition time(MAT) and detection error probability are evaluated via computer simulations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.10 s.340
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• pp.1-8
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• 2005

This Paper Proposes the algorithm for improving the Performance or symbol timing synchronization in hoc terrestrial DTV system. The Gardner algerian is used for symbol timing synchronization has good performance in multipath fading environment but degradation of performance is caused by jitter. Though the amount of jitter becomes more little as narrow bandwidth of loop Inter, convergence speed becomes slower. This paper propose the algorithm that averages out values of loop filter every certain time and gradually reduces the bandwidth of loop filter after estimating offset using this average for the high speed of convergence and reducing the met of jitter. The proposed algorithm has better performance with high speed of convergence and the amount of jitter than conventional method.