• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.4
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• pp.378-384
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• 2006

In this paper, the design and performance analysis of switched reluctance motor(SRM) according to the design parameters are researched for a traction drive. The parameters which are sensitive to the performance are examined and selected to have good performances. For the high performance of traction drive, some effective guide lines to have a good performance motor are suggested. The prototype machine is constructed to compare with the simulated and tested for the comparison of design results.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.40 no.2
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• pp.213-220
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• 2016

This research aims to develop core technologies for passive carrier (no power in carrier itself) transfer system. The technologies are passive levitation, propulsion, and guidance, which can be great benefits for semiconductor and display manufacturing industries. Passive maglev carrier is necessary to precise position control for quiet and stable transfer operation. However, the structural characteristics of carrier and the installation errors of gap sensors cause the pitch motion. Hence, the controller design in consideration of pitch motion is required. This study deals with the reduction control of carrier pitch motion. PDA controller and PDA controller with pitch control are proposed to compare the pitch angle analysis. The pitch angle and the levitation precision are measured by experiment. Finally, the optimized design of pitch controller is presented and the effects are discussed.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of IKEEE
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• v.16 no.1
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• pp.20-27
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• 2012

In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.6
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• pp.641-648
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• 2011

Off-gases emitted from the anode of a molten carbonate fuel cell (MCFC) at high temperatures for power generation are used as fuel in catalytic combustion. The heat generated in the catalytic combustor is utilized as the heat for the endothermic reaction required for steam reforming. Among the various operational conditions of the integrated reactor, we varied the inlet gas compositions of the catalytic combustor according to fuel utilization in the MCFC and the ratio of steam to carbon in the reformer. Subsequently, the thermal behaviors and reaction characteristics of the integrated reactor were investigated experimentally. The fundamental data from this experimental study will be useful for the design and fabrication of a more practical integrated reactor in the future.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.5
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• pp.259-267
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• 2001

칩의 집적도에 비례하여 설계검증 및 칩 제작 후의 결함점검은 갈수록 어려워지며 이러한 테스트 문제의 원초적 해결을 위하여 다양한 테스트설계 기술이 널리 개발되고 있다. 상위 수준의 테스트설계에서는 회로의 기능에 대해서는 알 수 있으나 구조에 대해서는 알 수 없고, 하위 수준의 테스트설계에서는 회로의 구조를 알 수 있으나 기능은 알 수 없다. 따라서 테스트 설계는 기능을 기술하는 상위 수준에서부터 고려되어 하위 게이트수준에서 스캔플립플롭을 선택하여야 최적화된 성능을 얻을 수 있다. 본 논문에서는 테스트용이도를 증진시키기 위해, 상위수준의 기능정보에 대해서는 테스트점을 삽입하여 제어흐름(control flow)을 변경하고, 상위 수준의 합성 후에 하위 수준에서 스캔플립플롭을 선택하여 다시 합성하는 상위.하위 수준에서 통합된 테스트 합성 기술을 제안한다. 실험결과 통합된 테스트 합성 기술이 대부분의 벤치마크 회로에서 높은 고장검출율을 보여주고 있다.

• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.580-584
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• 2017

본 논문에서는 얀센 메커니즘을 이용한 4족 보행 로봇의 설계와 라인 추적을 통해 목표지점까지 도달할 수 있도록 하는 센싱에 대해 보인다. 가장 핵심이라고 판단되는 구동부의 최적 설계를 위해 m.Sketch를 이용하여 GAC와 GL를 설정하였고, 최적 설계 후 다리 경량화를 통한 로봇 속도 개선 등의 문제는 차후에 다루기로 한다. 본 논문에서 언급되는 모든 구동부는 이론적 계산을 기초로 하여 CATIA 프로그램을 사용하여 제작되었으며, 과학상자를 이용한 여러 번의 구조변경 실험을 통해 최적의 설계를 찾는 것을 목표로 한다.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2011.11a
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• pp.666-669
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• 2011

The rupture disc shapes of bulkhead type pulse separation device(PSD) are designed for new dual pulse rocket motor. Before final design PSD, that three different rupture disc are tested and confirmed the performance of the discs. Through analyzing the test results the PSD decides, two rupture disc shapes with flow holes of eight circles and eight trapezoids.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.214-219
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• 2000

본 논문에서는 사용자 수준에서 시스템 호출을 제어하는 방법 및 구성을 제안하고, 이를 위해 유닉스 시스템 호출을 가로채는 방법을 기술한다. 제안된 방법은 유닉스의 소스 코드의 수정을 필요로 하지 않으므로, 동적으로 적용 및 변경이 가능하다. 또한, 시스템 호출 제어방법의 응용 모델로서, 사용자의 시스템 자원 접근을 제어하는 보안 모델로 설계된 UPS(Unix Protection System)에 대하여 기술한다. UPS의 성능 평가는 벤치마크 프로그램들의 수행을 통해 추가 부하(overhead)를 살펴본다. 실험 결과에 의하면 UPS를 사용한 경우는 사용하지 않은 경우보다 1$\sim$19%의 추가적인 시간이 소요되었다.