• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.33-40
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• 2005

This paper presents a structure of the searcher using a diversity in array antenna systems operating in the cdma2000 1x signal environments. The new technique exploits the fact that the In-phase and quadrature components of interferers can respectively be viewed as an independent gaussian noise at each antnna element in most practical cdma signal environments. The proposed PN acquisition scheme is a singles-dwell PN acquisition system consisting of two stages, that is, the searching stage and the verification stage. The searching stage independently correlates the receiver multiple signals with PN generator of each antenna element for obtaining the synchronous energy at the entire region. Then, the searching results of each antenna element are non-coherently combinind. The verification stage compares the searching energy with the optimal threshold, which is predesigned in the lock detector, and decides whether the acquisition is successful or fail. In this paper, we analyzed the effect of tile diversity order to determine the mean acquisition time. In general, it is known that the mean acquisition time significantly decrease as the number of antenna elements increases. But, as the diversity order goes up, the enhancement of the performance is saturated. Therefore, to decrease the mean acquisition time of the searcher, we must design the optimal array antenna systems by considering the operating SNR range of the receiver, the probability of detection $P_D$ and that of false alarm $P_{FA}$ . The Performance of the proposed PN acquisition scheme is analyzed in frequency selective Rayleigh fading channels. In this paper, the effect of the number of antenna elements on PN acquisition scheme is shown according to the probability of detection $P_D$ and that of false alarm $P_{FA}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of KIISE
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• v.44 no.3
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• pp.246-252
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• 2017

In this paper, we present an algorithm that computes a minimum-width color spanning axis-parallel rectangular annulus. A rectangular annulus is a closed region between a rectangle and its offset, and it is thus bounded by two rectangles called its outer and inner rectangles. The width of a rectangular annulus is determined by the distance between its outer and inner rectangles. Given n points in the plane each of which has one of the prescribed k colors, we call a rectangular annulus color spanning if it contains at least one point for each of the k colors. Prior to this work, there was no known exact algorithm that computes a minimum-width color-spanning rectangular annulus. Our algorithm is the first to solve this problem and it runs efficiently in $O((n-k)^3nlogn)$ time.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• Korean Journal of Remote Sensing
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• v.27 no.1
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• pp.9-15
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• 2011

Since PAN(panchromatic) and MS(multispectral) imagery of pushbroom scanner have the offset between PAN and MS CCD(charge coupled device) in the focal plane, PAN and MS images are acquired at different time and angle. Since clouds are fast moving objects, they should lead mis-registration problem with wrong matching points on clouds. The registration of cloudy imagery to recognize and remove the contamination of clouds can be categorized into three classes: (1) cloud is considered as nose and removed (2) employing multi-spectral imagery (3) using multi-temporal imagery. In this paper, method (1) and (3) are implemented and analysed with cloudy pushbroom scanner images.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.109-114
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• 2015

Frame synchronization is achieved by correlation between received symbols and a preamble pattern which is periodically appended at a frame header. In this paper, we deal with a frame detection method complaint with satellite-based DVB-S2 system. In DVB-S2, frame synchronization is performed under the low signal-to-noise ratio(SNR), a large frequency offset which can be up to 20% of a symbol transmission rate and unknown modulation schemes ranging from QPSK to 32-APSK. In this environment, we propose a method combining differential correlation based on SOF and PLSC with an accumulated correlation method for the detection of frame structures. In addition, detection performances about mean acquisition time(MAT) and detection error probability are evaluated via computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.488-498
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• 2005

The DAB(Digital Audio Broadcasting) service which is based on the Eureka-147 of Europe is developed to DMB(Digital Multimedia Broadcasting) service that is divided into Terrestrial DMB and Satellite DMB. The Satellite DMB is a new broadcasting service, which will service multi-channel multimedia broadcasting by the portable receiver or the vehicle receiver. In this paper, we consider that link level performance of satellite DMB system A which is based on the COFDM(Coded Orthogonal Division Multiplexing). It uses the OFDM method which is sensitive to nonlinearity, so we analyze the effect of the HPA(High Power Amplifier) nonlinearity. And then we define the appropriate back-off value by performing the link level simulation considering back-off effect. Also we consider the effect of frequency and time offset, and then confirm the overall link level performance by analyzing and verifying a suitable synchronization method for satellite DMB system A.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.69-78
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• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.