• Clean Technology
• /
• v.18 no.3
• /
• pp.320-324
• /
• 2012

In the present study, the discharge characteristics of a lithium-ion battery was evaluated to calculate the rate of heat generation under various discharge rates by mathematical modeling. The modeling and simulation of a pseudo-two dimensional ionic transport system for governing Butler-Volmer equation were carried out by using FEMLAB as a PDE (partial differential equation) solver, where the discharge rate was changed from 5 $A/m^2$ to 25 $A/m^2$. The computational results showed that the concentration of consumed solid-phase lithium at the surface of electrode was increased with increasing discharge rates. While the resulting diffusion limitation occurred shortly, it increased the rate of heat generation even more rapidly for the internal voltage to approach the cutoff voltage of the lithium-ion battery.

• Proceedings of the KIPE Conference
• /
• 2013.07a
• /
• pp.159-160
• /
• 2013

본 논문에서는 백열등 조도 조절용 조광기에 호환 가능한 LED 구동회로를 제안한다. 조광기와 일반적인 LED 구동회로를 연결할 경우 트라이악(Triac)의 오동작에 의해 플리커(Flicker) 현상이 발생하는 문제점을 지니고 있다. 트라이악의 오동작을 방지하기 위해서는 트라이악에 일정 크기 이상의 전류가 인가되어야 하며 이를 만족하기 위한 조광기 호환회로가 필수적이다. 이러한 호환회로로써 수동 블리더(Passive Bleeder)는 전 동작 구간에서 전력소모가 발생하는 단점을 지니고 있다. 본 논문의 제안회로는 역률 만족을 위 해 Valley-fill 회로를 적용하였으며 트라이악의 오동작 시점을 정확히 검출하여 새로운 방식의 능동 블리더(Active Bleeder)를 적용함으로써 조광기의 오동작을 방지하면서 수동 블리더에 비해 효율이 개선되는 장점을 지닌다. 또한, Valley-fill과 인덕터를 적용한 1단 구성으로 효율개선 및 역률 개선의 장점과 입력 전류 리플의 감소로 인한 EMI 노이즈 저감 효과를 나타낸다. 본 논문에서는 제안된 회로의 타당성을 검증하기 위하여 13W급 조명용 LED 구동회로의 시작품 제작을 통해 그 우수성을 확인한다.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.13 no.4
• /
• pp.56-68
• /
• 2014

This paper presents an experiment on the modeling, analysis, prediction and optimization of machining parameters used during the turning process of the low-carbon steel known as ST40. The parameters used to develop the model are the cutting speed, the feed rate, and the depth of the cut. The experiments were carried out under various conditions, with three level of parameters and two different treatments for each level (with and without a lubricant), to determine the effects of the parameters on the surface roughness and electric current consumption. These effects were investigated using response surface methodology (RSM). A second-order model is used to predict the values of the surface roughness and the electric current consumption from the results of experiments which collected preliminary data. The results of the experiment and the predictions of the surface roughness and electric current consumption under both treatments were found to be nearly identical. This result shows that the feed rate is the main factor that influences the surface roughness and electric current consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.835-838
• /
• 2011

This paper presented an occupancy-based smart plug system for appliance energy saving in home. We measured current consumption of appliances in real time using smart plugs, and check the occupation of residents using occupancy sensors installed on the door. The proposed system saves energy to switch off the supply power of unnecessary usages in the unoccupied spaces. Experiments conducted have shown that current usage of appliances can be measured by using smart plugs and presence can be checked by using occupancy sensors.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.6
• /
• pp.18-24
• /
• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.7 s.361
• /
• pp.41-46
• /
• 2007

A novel post-linearization technique is proposed for CMOS cascode low noise amplifier (LNA). The technique uses dual common gate FETs one of which delivers the linear currents to a load and the other one sinks the $3^{rd}$ order intermodulation currents of output currents from the common source FET. Selective current branching can be implemented in $0.18{\mu}m$ CMOS process by using a thick oxide FET as an IM3 sinker with a normal FET as a linear current buffer. A differential LNA adopting this technique is designed at 2.14GHz. The measurement results show 11dBm IIP3, 15.5dB power gain and 2.85dB noise figure consuming 12.4mA from 1.8V power supply. Compared with the LNA with turning off the IM3 sinker, the proposed technique improves the IIP3 by 7.5 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.85-96
• /
• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.6
• /
• pp.55-66
• /
• 2016

Power gating is one of effective techniques for reducing leakage current in semiconductor chip. However, power gating cell (PGC) which is used to switch the power source causes performance degradation and the associated reliability problem by increasing IR drop. However, the newly raised problem caused by different scaling properties between gates and metal wires demands additional considerations in power gating design. In this paper, we propose a robust cell placement based power gating design method for reducing the area for power gating cell and metal routing thus to meet IR drop requirement. Experimental results by applying the proposed techniques on the application processor for smartphone fabricated in 28nm CMOS process show that power gating cell area is reduced by 16.16% and maximum IR drop value is also decreased by 8.49% compared to existing power gating cell placement techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.1-7
• /
• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.11
• /
• pp.2541-2547
• /
• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.