• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.73-81
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• 2011

As high speed digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information, it can bring about many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge to implement a system. Especially, the noise sources in high frequency digital systems include the noise in power supply, ground and packaging, and they destroy the fidelity of signals. Therefore PCB design with impendence matching is needed to improve fidelity of signal in H/W. In this paper, we have developed an impedance control and analysis tool for multi-layer PCB design, and simulates the tracks controlled impedance with the test coupon. So, it can save the design time and support the economical PCB design.

• Korean Journal of Optics and Photonics
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• v.16 no.1
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• pp.34-42
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• 2005

This paper presents the optimum initial design containing the first and third order properties of the three-group zoom system using lens modules, and the real lens design of the system. The optimum initial design with focal length range of 4.3 mm to 8.6 mm is derived by assigning appropriate first and third order quantities to each module along with the specific constraints required for the system. An initial real lens selected for each group has been designed to match its focal length and the first orders into those of the each lens modules, and then combined to establish an actual zoom system by adjusting the air space between the groups at all zoom positions. The combination of the separately designed groups results in a system which satisfies the first order properties of the zoom system composed of the original lens modules. As a result, by residual aberration correction, we could obtain a zoom system useful in compact digital zoom cameras and mobile phone cameras employing the rear focus method.

• Journal of Advanced Navigation Technology
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• v.17 no.3
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• pp.292-297
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• 2013

In this paper, The design of digital circuits for chaotic composition function which is used for the key-stream generator is studied in this work. The overall design concept and procedure due to the mathematical model of chaotic key-stream generator is to be the explained in detail, and also the discretized truth table of chaotic composition function is presented in this paper. consequently, a composition state machine based on the compositive map with connecting two types of one dimensional and two dimensional chaotic maps together is designed and presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.2
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• pp.135-140
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• 2014

In this paper, we describe the contents of noise characteristic enhancement using digital filtering to the motion vector in the pattern noise of optical mouse. The designed circuit is implemented to enhance the smoothing and trembling with filtering and averaging of x, y motion vector before PS2 or USB output. The function is verified by using FPGA and the performance is measured by the fabricated chip using $0.35{\mu}m$ standard CMOS process. The system clock is 6MHz and the motion vector has the range of +6 to -6 per 1/1700sec. It is tested using the Cartesian robot to measure the noise characteristic enhancement.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2149-2151
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• 2003

본 논문에서는 마이컴(PIC16C74)과 Tabu 탐색법 및 지능기법(퍼지 및 신경회로망)을 이용하여 고정밀 제어 및 강인한 제어 성능을 가지는 초소형 DC 모터용 지능형 제어기를 개발하였다. 이를 위해 마이컴(PIC16C74)를 이용한 지능형 제어 알고리즘을 개발하고, 초소형 DC 모터용 드라이브 회로 설계 및 제작하였다. 개발한 초소형 DC 모터 지능형 제어기는 디지털 자동 용접캐리지에 적용할 예정이며, 다른 응용 분야로써는 자동배수장치, 반도체 분야, 산업용 로봇 분야 및 조립자동화 시스템 분야 등에 사용되는 구동모터에 적용함으로서 정밀도와 외부의 잡음에 대한 영향을 경감시켜 안정성과 효율향상 및 에너지절약이 가능할 것이다.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.