• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6C
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• pp.619-625
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• 2009

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.1
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• pp.65-71
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• 2006

In this paper, a novel motor control method is proposed to improve the performance of sensorless drive of BLDC motors. In the terminal voltage sensing method, which is a great portion of sensorless control, a precise rotor position cannot be obtained when excessive input is applied to the drive during synchronous operation mode. Especially in the transient state, the response characteristic decreases. To cope with this problem, the unknown input (back-EMF) is modelled as the additional state of system in this paper. Taking into account the disturbance adopted by the back-EMF, the observer can be obtained by the augmented system equation. An algorithm to detect the back-EMF of the BLDC motor using the state observer is constructed. As a result, the novel sensorless drive of BLDC motors that can strictly estimate rotor position and speed is proposed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.3
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• pp.14-21
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• 2010

For the ubiquitous healthcare environment, real-time measurement of biomedical signals and accuracy of the measured biomedical information are very important. In addition, it is important to develop a healthcare device with low power In this paper, the synchronized pulse in a heartbeat was detected from the radial artery using the piezo film sensor, in order to eliminate inconvenience to wear a pulse detection finger probe. We can get a best output after applying the adaptive noise canceller using two piezo film sensor signals, pulse signal having motion artifacts and motion artifacts reference signal. To detect heartbeat, we use maximum point detection method from pulse removed motion artifacts.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.62-67
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• 1999

Phase rotational is a practical problem in the implementation of coherent demodulation. Large phase noise may intorduce phase rotation in the demodulator which results in repeated decision errors. This paper presents a simple and yet very efficient technique in building a carrier recovery loop which minimizes the phase rotation by improving the stability of the decision-directed carrier recovery loop. Simulation shows this novel technique improves the performance of the carrier recovery loop as well as stability.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.9
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• pp.453-458
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• 2001

This paper presents a new vector control algorithm of the surface mounted permanent magnet motor (SMPMM) without any rotational tranceducer. Originally, SMPMM does not have any magnetic saliency in structure, but it has a little magnetic saliency due to the saturation by the flux of the permanent magnet. Moreover, it varies according to the load conditions and the control performance of schematics using the saliency can be easily degraded. To prevent it and to improve the performance of the proposed algorithm, the saliency of a SMPMM under various load conditions is analyzed. In the proposed algorithm, the saliency or the impedance difference related to the saliency is utilized in order to estimate the position and speed of the rotor. And the high frequency signal is injected into the motor to measure the impedance difference and also to enhance the control performance of the system. The experimental results verify the performance of the proposed sensorless algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.449-455
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• 2022

In this paper, we propose a position measuring system using trilateration based on the illuminance of a light-emitting diode (LED). Three LEDs are located on the ceiling of the virtual space, and each fixed coordinate is inputted to the monitoring program, and Length to the illuminance sensor is drawn through the relational expression of the length and illuminance value from the respective LED. Based on the derived length, the trilateration method is used to find object location information in virtual space. By using the least square equation to minimize the error of the length drawn to trilateration, the error is reduced to the utmost. Unlike the existing indoor positioning system using visible light communication (VLC), the proposed system does not require synchronization between the transmitter and the receiver, so the system can be configured simply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.10
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• pp.41-48
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• 2008

This paper proposes a three-phase Z-source dynamic voltage restorer (Z-DVR) to mitigate the voltage sag for the critical loads. The proposed system is composed of passive filter and Z-source topology inverter. As an ESS(Energy Storage System) of the proposed system is employed the Proton Exchange Membrane Fuel Cells (PEMFC). To calculate and control the harmonics and compensation voltage, $i_{d}-i_{q}$ theory in dq rotating reference frame and PI controller are used. In case that three-phase voltage sags occurred, a PSIM simulation was done for the performance comparison of the conventional method employed battery stacks and proposed method. As a result, considering the voltage compensation performance, each method was nearly similar. Also, the compensation performance and the %THD(%Total Harmonic Distortion) result under the various source voltage conditions (sag or swell) were presented and discussed to show the performance of the proposed system.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.1
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• pp.82-89
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• 2014

This paper discusses the methods for reducing the sampling time quantization errors of the body dither type ring laser gyroscope. A ring laser gyroscope has the angle quantization error which is generated by the frequency counting method of the laser beat signal and sampling time quantization error which is generated by the demodulation method for eliminating the body dithering in which the sampling periods are fitted to the dither periods. Generally, because the dither periods are longer than the calculation periods of the inertial navigation system, vehicle navigation errors are produced by long time attitude update missing during the vehicle move with a high dynamical motion. In this paper, the double demodulation method is proposed for reducing the sampling time quantization error and its effects under the dynamic situation are confirmed by simulation.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.49-57
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• 2009

The camera electronics in the KOMPSAT-3 payload provides the several control clocks in order to move the charges, which are converted from the light in the pixel, in the vertical and horizontal direction. Generally, the control clocks depend on the CCD internal design in the system. The KOMPSAT-3 payload uses the CCD controlled by 3-phase vertical clocks and 4-phase timing. The camera generates the various clocks such as the vertical clocks, the horizontal clocks, the summing clocks, the reset clocks and so on. The vertical clocks are deeply related to the camera performance and synchronized with satellite scan-rate even though they are relatively slow. Also, it gives the horizontal clocks without distortion under the very fast pixel-rate. This paper shows the design and simulation of the CCD clocks driver for the KOMPSAT-3 payload.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.