The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Parallel Processing Architecture for Parity Checksum Generator Complying with ITU-T J.83 ANNEX B

ITU-T J.83 ANNEX B의 Parity Checksum Generator를 위한 병렬 처리 구조

  • 이종엽 (광주과학기술원 정보기전공학부, 통신시스템연구실) ;
  • 홍언표 (광주과학기술원 정보기전공학부, 통신시스템연구실) ;
  • 하동수 (광주과학기술원 정보기전공학부, 통신시스템연구실) ;
  • 임회정 (전남대학교 치의학연구소)
  • Published : 2009.06.30
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Abstract

This paper proposes a parallel architecture of a Parity Checksum Generator adopted for packet synchronization and error detection in the ITU-T Recommendation J.83 Annex B. The proposed parallel processing architecture removes a performance bottleneck occurred in a conventional serial processing architecture, leading to significant decrease in processing time for generating a Parity Checksum. The implementation results show that the proposed parallel processing architecture reduces the processing time by 83.1% at the expense of 16% area increase.

이 논문은 ITU-T Recommendation J.83 Annex B에서 패킷 동기화와 에러 검출을 위해 사용된 패리티 체크섬 생성기의 병렬 구조를 제안한다. 제안된 병렬 처리 구조는 기존의 직렬 처리 구조에서 일어나는 병목현상을 제거하여 패리티 체크섬을 생성하는데 필요한 처리 시간을 상당히 줄여준다. 실험 결과는 제안된 병렬 처리 구조가 16%의 면적증가로 처리 속도를 83.1%나 줄일 수 있다는 것을 보여준다.

Keywords

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