• Title/Summary/Keyword: 동기검출기

Search Result 188, Processing Time 0.022 seconds

Design of Digital Phase-locked Loop based on Two-layer Frobenius norm Finite Impulse Response Filter (2계층 Frobenius norm 유한 임펄스 응답 필터 기반 디지털 위상 고정 루프 설계)

  • Sin Kim;Sung Shin;Sung-Hyun You;Hyun-Duck Choi
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.19 no.1
    • /
    • pp.31-38
    • /
    • 2024
  • The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

The Control Method of In-Wheel PMSM for Electric Scooter using Speed Observer (속도 관측기를 이용한 전기스쿠터용 IN-WHEEL 영구자석 동기 전동기의 제어 방법)

  • Son, Tae-Sik;Lee, Yong-Kyun;Kim, Hag-Wone;Cho, Kwan-Yuhl;Mok, Hyung-Soo
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.16 no.2
    • /
    • pp.130-136
    • /
    • 2011
  • This paper presents the torque control algorithm of a permanent magnet synchronous motor(PMSM) for an electric scooter. The volume of the in-wheel type motor is restricted due to the complicated mechanical structure in wheel of an electric scooter, so the hall sensors instead of resolver and encoder for the rotor position sensors are installed. In this paper, the rotor speed and position are estimated from the speed estimator for vector control of a PMSM with hall sensors. The motor starts to rotate at standstill in BLDC mode with 120 degree conduction. After start up, the operating mode is changed to the vector control with maximum torque per ampere(MTPA) operation at low speeds and flux weakening control at high speeds. The performance of the proposed control algorithm is verified through the experiment in the electric scooter.

A High-Performance Position Sensorless Motion Control System of Reluctance Synchronous Motor with Direct Torque Control (직접토크제어에 의한 위치검출기 없는 릴럭턴스 동기전동기의 위치 제어시스템)

  • 김동희;김민회;김남훈;배원식
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.7 no.5
    • /
    • pp.427-436
    • /
    • 2002
  • This paper presents an implementation of high-dynamic performance of position sensorless motion control system of Reluctance Synchronous Motor(RSM) drives for an industrial servo system with direct torque control(DTC). The problems of high-dynamic performance and maximum efficiency RSM drives controlled by DTC are saturation of stator linkage flux and nonlinear inductance characteristics with various load currents. The accurate estimation of the stator flux and torque are obtained using stator flux observer of which a saturated inductance $L_d$ and $L_q$ can be compensated by adapting from measurable the modulus of the stator current and rotor position. To obtain fast torque response and maximum torque/current with varying load current, the reference command flux is ensured by imposing $I_{ds} = I_{qs}$. This control strategy is proposed to achieve fast response and optimal efficiency for RSM drive. In order to prove rightness of the suggested control algorithm, the actual experiment carried out at $\pm$20 and $\pm$1500 rpm. The developed digitally high-performance motion control system shown good response characteristic of control results and high performance features using 1.0kW RSM which has 2.57 Ld/Lq salient ratio.

Implementation of a Window-Masking Method and the Soft-core Processor based TDD Switching Control SoC FPGA System (윈도 마스킹 기법과 Soft-core Processor 기반 TDD 스위칭 제어 SoC 시스템 FPGA 구현)

  • Hee-Jin Yang;Jeung-Sub Lee;Han-Sle Lee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
    • /
    • v.17 no.3
    • /
    • pp.166-175
    • /
    • 2024
  • In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

Parallel Data Extraction Architecture for High-speed Playback of High-density Optical Disc (고용량 광 디스크의 고속 재생을 위한 병렬 데이터 추출구조)

  • Choi, Goang-Seog
    • Journal of Korea Multimedia Society
    • /
    • v.12 no.3
    • /
    • pp.329-334
    • /
    • 2009
  • When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

  • PDF

Dead Time Compensation of Grid-connected Inverter Using Resonant Controller (공진 제어기를 이용한 계통 연계형 인버터의 데드타임 보상)

  • Han, Sang-Hyup;Park, Jong-Hyoung;Kim, Heung-Geun;Cha, Honn-Yong;Chun, Tea-Won;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.16 no.6
    • /
    • pp.569-576
    • /
    • 2011
  • This paper proposes a new dead time compensation method for a PWM inverter. Recently, PWM inverters are extensively used for industry applications, such as ac motor drives, distributed grid-connected systems and a static synchronous compensator (STATCOM). Nonlinear characteristics of the switch and the inverter dead time cause a current distortion and deterioration of power quality. The dominant harmonics in the output current are the $5^{th}$ and $7^{th}$ harmonics in the stationary frame, and the $6^{th}$ harmonics in the synchronous rotating frame. In this paper, a resonant controller which compensates the $6^{th}$ harmonics in the synchronous rotating frame is proposed. This method does not require any off-line experimental measurements, additional hardware and complicated mathematical computations. Furthermore, the proposed method is easy to implement and does not cause any stability problem.

Mobile Camera Processor Design with Multi-lane Serial Interface (멀티레인을 지원하는 모바일 카메라용 직렬 인터페이스 프로세서 설계)

  • Hyun, Eu-Gin;Kwon, Soon;Lee, Jong-Hun;Jung, Woo-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.7 s.361
    • /
    • pp.62-70
    • /
    • 2007
  • In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

Design and Performance Improvement of a Digital Tomosynthesis System for Object-Detector Synchronous Rotation (물체-검출기 동기회전 방식의 X-선 단층영상시스템 설계 및 성능개선에 관한 연구)

  • Kang, Sung-Taek;Cho, Hyung-Suck;Roh, Byung-Ok
    • Journal of Institute of Control, Robotics and Systems
    • /
    • v.5 no.4
    • /
    • pp.471-480
    • /
    • 1999
  • This paper presents design and performance improvement of a new digital tomosynthesis (DTS) system for object-detector synchronous rotation. Firstly, a new DTS system, called OSDR (Object-Detector Synchronous Rotation) is suggested and designed to acquire X-ray digital images. Secondly, the shape distortion of DTS images generated by an image intensifier is modeled. And a new synthesis algorithm, which overcomes the limitations of the existing synthesis algorithm, is suggested to improve the sharpness of the synthesized image. Also an artifact analysis of the DTS system is performed. Thirdly, some performance indices, which evaluate quantitatively performance improvement, are defined. And the experimental verification of the performance improvement is accomplished by the ODSR system newly designed. The advantages of the ODSR system are expressed quantitatively, compared with an existing system.

  • PDF

Running Inverse for Implementing Decorrelating Detectors in Synchronous DS/CDMA Systems

  • Joo, Jung-Suk;Lee, Yong-Hoon
    • Journal of IKEEE
    • /
    • v.2 no.2 s.3
    • /
    • pp.294-298
    • /
    • 1998
  • We propose an efficient method for updating the inverse of the signature waveform cross-correlations (SWC) matrix when the number of users in the synchronous direct-sequence code-division multiple-access (DS/CDMA) system changes. It is shown that the computational complexity of the proposed method is $O(n^2)$ in which n represents the number of active users in the system.

  • PDF

A simple computational algorithm of ML optimum multiuser detector for synchronous code division multiple access channels (동기화된 부호 분할 다원 접속 채널을 위한 ML 최적 다중 사용자 검출기의 간단한 계산 알고리즘)

  • 권형욱;최태영;오성근
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.5
    • /
    • pp.1-9
    • /
    • 1996
  • In this paper, we propose an efficient computational algorithm that can reduce significantly the computational complexity of the ML optimum multiuser detector known as the most excellent detector in synchronous code division multiple access channels. The proposed detector uses the sequential detection algorithm based on the alternating maximization appraoch to obtain the ML estimates. As initial estimates for this sequential algorithm, we can use the estimated values obtained by the conventional single-user detector, the linear decorrelating multiuser detector, or the decorrelating decision-feedback muliuser detector, the linear decorrelating multiuser detector, or the decorrelating decision-feedback multiuser detector. We have performed computer simulations in order to see the convergence behaviors and the detection performance of the propsoed algorithm in terms of initial algorithms and the number of users, and then to compare the computational complexity with that of the ML optimum multiuser detector. From the results, we have seen that the proposed alternating maximization detector has nearly equal detction performance with that of the ML optimum multiuser detctor in only a few iteration.

  • PDF