• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1667-1670
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• 2004

x86기반 임베디드 리눅스 시스템의 저장장치로 단일-칩 플래시 디스크인 DOC(DiskOnChip) 시스템이 많이 사용되고 있다. 본 연구에서는 DOC 스스로 부팅하도록 부팅이미지, 커널이미지, 루트파일시스템을 설치하는 과정을 설명한다. DOC는 자체 기능으로 에러탐색 및 수정기능과 파일시스템으로 TrueFFS가 인터페이스로 동작한다. 또한, 구성된 DOC 저장 시스템에 GUI 구현할 수 있도록 Qt-E 계층을 추가하여 시스템 개발자는 단지 어플리케이션을 설치함으로써 쉽게 임베디드시스템을 구성할 수 있다.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• Journal of the Korea Society of Computer and Information
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• v.16 no.11
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• pp.1-8
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• 2011

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.119-122
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• 2011

GPS 의 사용이 어렵거나 불가능한 실내 환경 등에서 사물이나 사람의 위치를 카메라가 추적할 수 있도록 하는 문제에 대해 많은 연구가 진행되고 있다. 이를 가능 하도록 하기 위해서는 작은 크기의 이동 장치와 센서 노드간 밀접한 통신이 필수이다. 본 연구에서는 무선 수신/송신 장치인 센서 노드를 이용하여 고정 된 수신-센서 노드와 이동 송신 노드를 이용하여 효율적이고 다수의 목표물을 추적할 수 있는 위치 추적 시스템을 설계하는 기법을 연구하고, 실제 알고리즘을 구성하였다. 그리고 휴대성을 높이고 위치 추적 알고리즘 계산을 효율적으로 할 수 있도록 알고리즘을 SoC(단일칩 시스템, System on Chip)로 설계하여 시스템의 확장성을 확보하는 방법을 제시하고자 한다.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.801-805
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• 2009

Hardware based dynamic voltage and frequency scaling is a promising technique to reduce power consumption in a globally asynchronous locally synchronous system such as a homogeneous or heterogeneous multi-core system. In this paper, FPGA prototype design of hardware based dynamic frequency scaling is proposed. The proposed techniques are applied to a FIFO based multi-core system for a software defined radio and Network-on-Chip based hardware MPEG2 encoder. Compared with a references system using a single global clock, the first prototype design reduces the power consumption by 78%, but decreases the performance by 5.9%. The second prototype design shows that power consumption decreases by 29.1% while performance decreases by 0.36%.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.9-11
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• 1999

3차원 그래픽 랜더링 파이프라인(3D Graphics Rendering Pipeline)은 크게 지오메트리 프로세싱(Geometry Processing)과 레스터라이제이션(Rasterization)으로 구성되어 있다. 본 논문에서는 래스터라이저와 프레임버퍼사이의 대역폭으로 인한 병목점을 분석하고, 그 한계를 극복해 낼 수 있도록 프로세서 메모리 집적구조를 이용하여 랜더링 시스템을 설계, 성능 분석한다. 프레임버퍼의 집적으로 인한 메모리 대역폭을 이용하기 위해, 각 픽셀 처리에 필요한 로직을 포함하는 SIMD 타입의 픽셀 처리 프로세서가 메모리 어레이와 밀결합(tightly coupled)된다. 제안하는 구조는 래스터라이저 로직과 프레임 버퍼가 단일 칩으로 구성되었고, 텍스쳐 매핑, 범프 매핑, 안티알리아싱, 깊이 버퍼를 지원하며 초당 5백만 이상의 삼각형을 처리할 수 있는 고성능 랜더링 시스템이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1349-1355
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• 2016

It should guarantee high reliability and ultra low latency communication. Additionally, it should support connection between massive devices. As one of estimated scenarios for 5G mobile communication, mobile devices and sensors using low data rate wireless communication will increase. For communication of these devices, single-carrier system can be considered. In order to satisfy these requirements, in this paper, we propose CDMA (Code Division Multiple Access) system using complex spreading and Multi-level BPSK(Binary Phase Shift Keying). The proposed system spread transmit symbol by using chip code consisted of real and imaginary number. As simulation results, we can confirm that although the proposed system has 3dB lower BER (Bit Error Rate) performance than conventional CDMA system, the proposed system can support 2 times more users in comparison with conventional CDMA system.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.768-772
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• 2008

Today's microprocessor normally includes several processing cores to reduce the energy consumption without losing performance. In this paper, data transfer ordering mechanism can be efficiently used for cache coherence solution in unidirectional ring interconnect. RING-DATA ORDER combines the simplicity of GREEDY-ORDER and the performance of RING-ORDER. RING-DATA ORDER can be easily applicable to multicore processor with unidirectional ring interconnect.