Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
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Implementation and Verification of JPEG Decoder IP using a Virtual Platform

가상 플랫폼을 이용한 JPEG 디코더 IP의 구현 및 검증

  • Jung, Yong-Bum (School of Electrical Engineering, University of Ulsan) ;
  • Kim, Yong-Min (School of Electrical Engineering, University of Ulsan) ;
  • Hwang, Chul-Hee (School of Electrical Engineering, University of Ulsan) ;
  • Kim, Jong-Myon (School of Electrical Engineering, University of Ulsan)
  • 정용범 (울산대학교 전기공학부) ;
  • 김용민 (울산대학교 전기공학부) ;
  • 황철희 (울산대학교 전기공학부) ;
  • 김종면 (울산대학교 전기공학부)
  • Received : 2011.02.05
  • Accepted : 2011.04.19
  • Published : 2011.11.30
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Abstract

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

하나의 제품에 다양한 기능들이 복합적으로 통합하는 단일칩시스템 (System-on-a-Chip, SoC)의 설계 요구가 증가하는 반면, 시장이 요구하는 적기 출하 시점은 점점 짧아지고 있다. 따라서 이러한 요구를 만족시키기 위해서 소프트웨어와 하드웨어를 통합하여 검증하는 것이 무엇보다 중요하다. 이러한 하드웨어-소프트웨어 통합 검증을 조기에 수행하는 방법으로 IP(intellectual property) 재사용을 통한 가상 플랫폼 기반 설계 방법이 널리 연구되고 있다. 본 논문에서는 기존 ARM프로세서 기반 S3C2440A 시스템을 가상 플랫폼을 이용하여 재설계하고, JPEG 디코더를 S3C2440A 가상 플랫폼에 구현하여 성능을 평가하였다. 또한, ARM 프로세서 기반 인라인 어셈블리어를 이용하여 JPEG 디코더를 최적화하는 기법을 소개하였고, 이를 가상 플랫폼에 구현하여 성능 향상을 검증하였다. 이러한 가상 플랫폼 기반 설계를 통해 하드웨어 및 소프트웨어의 통합 검증이 가능하고, 시장 적기 출하(Time-to-Market) 요구에 신속히 대처할 수 있다.

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