• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.269-270
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• 2015

본 논문에서는 GaN FET과 같이 고주파 스위칭이 가능하나 턴-온 문턱전압이 매우 낮은 전력반도체 소자의 안정적 구동을 위해 기생성분을 최소화 할 수 있는 PCB Layout 설계 방법에 대해 고찰한다. PCB Track의 길이 및 배치에 따른 기생 인덕턴스 등의 기생성분을 정량적으로 분석하고, Faulty 턴-온에 가장 직접적인 문제를 야기하는 ac-loop 인덕턴스 최소화 설계 방법을 제시하며 실험으로 검증한다.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.55-56
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• 2016

무선전력전송 시스템은 대기전력과 안전 문제로 인해 수신부의 존재를 판단하는 알고리즘이 필요하다. 현재 전계결합을 이용한 무선전력전송 시스템이 연구되고 있지만 아직 송 수신부 확인에 대한 연구는 활발하지 않다. 본 논문에서는 거리나 압력 센서를 더하지 않고 기존 전극의 기생커패시턴스를 이용해 부하 유무를 감지하는 방법을 제안한다. 송신부의 두 전극은 수신부가 분리됐을 때와 비교했을 때 수신부가 완전 정렬된 경우 커패시턴스 값이 약 9배 증가하므로 일반적인 마이크로프로세서의 내부 저항과 본 기생커패시터의 계단파 응답을 이용하면 부하의 존재유무를 판단할 수 있다. 그리고 마이크로프로세서를 통해 분리 시와 완전정렬 시에 기생커패시턴스 값을 LCR 미터와 비교했을 때 각각 오차율 5.5%, 6.8%로 측정하고 이 값을 이용해 수신부 감지 알고리즘을 성능을 검증하였다.

• Korean journal of applied entomology
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• v.14 no.3 s.24
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• pp.137-140
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• 1975

Field experiments on red-pepper were conducted in Suweon area during 1972-1974 to determine the seasonal fluctuation of Heliothis assulta H. using black light traps and direct counts. Adult moths emerged in late May, and showed three peaks of fluctuation from late June to middle July, from middle August to late August, and in mid-September. Eggs were first discovered in the field in early July, with peak incidence Iron late August to early September. Larval peaks occurred in late July to early August, in late August and mid-September to mid-October Initial hatching in the field occurred in early July. The numbers of the first larval generation were the highest. The parasitization ratio of Trichogramma spp. on eggs averaged 51 percent during mid-July to mid-September. The numbers of Trichogramma spp. emerging from one tobacco bud-worm egg ranged from one to four, but in most cases one or two egg parasitizing wasps emerged.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.2
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• pp.101-107
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• 2002

High performance packages must protect circuits from the internal leakaged-electromagnetic fields as well as the surrounding. In this paper, we characterized an electromagnetically-shielded millimeter-wave ceramic package from 20 to 40 ㎓ using FEM(Finite Element Method). From these calculation results, the parasitic resonance is observed at 33.4 ㎓. We use metal-filled via-holes at the ceramic package walls and resonance has been suppressed in a frequency range from 20 to 40 ㎓. These calculation results will be helpful for MMIC packaging using electromagnetically-shielded millimeter-wave ceramic packages.

• Journal of IKEEE
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• v.24 no.3
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• pp.845-852
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• 2020

Developing standard cells for 3nm and beyond requires significant advances in the device and interconnect technology. Thus, it is very important to quantify the impact of the new technology in various aspects. In this paper, we perform a through analysis on the impact of Buried Power Rail (BPR) and Complementary FET (CFET) in the perspective of cell area and parasitics such as capacitance. We emphasize that CFET is a technology that realizes 4T and beyond for standard cell designs, but significant capacitance increases (+18.0%), compared to its counterpart technology (FinFET) cell, due to the increase of cell height in the Z-direction.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.959-964
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• 2018

In this paper, it was firstly confirmed that the drain current of the depleted SOI MOSFET operated in the high frequency response delay occurs by the inductive parasitic. Depleted SOI MOSFET cannot be applied as a conventional high-frequency MOSFET model because the response delay of the drain current is generated in accordance with the drain voltage fluctuation. This response delay may be described as a non-quasi-static effect, and the SOI MOSFET generated the response delay by the inductive parasitics compared to typical MOSFET. It is confirmed that depleted SOI MOSFET's RF characteristics can be well reproduced with the proposed method including the drain current response delay.

• Parasites, Hosts and Diseases
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• v.30 no.3
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• pp.169-176
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• 1992

In order to compare the intraspecific variation in host-parasite relationship of Clonorchis sinensis, six strains of inbred mice, ICR, DDY, GPC, BALB/c, nude and DS, were infected orally with 20 metacercariae of C. sinensis. The biologic incubation period of C. sinensis was the shortest in DDY mice, 21.2 days in average, followed by GPC 21.4, BALB/c and DS 23.2, ICR and nude 23.4 days, respectively. The fertile period of the cuke was also the longest in the DDY strain, 164 days on average, followed by GPC 132, BALB/c 97, nude 37, DS 32 and ICR 28 days. The egg-laying capacity of the cuke in DDY and GPC was relatively high and stable compared with the other four strains of mice. It was found that there are intraspecific variations in biologic incubation period, fertile period, and fecundity of C. sinensis. The DDY mouse is likely to be the most suitable experimental animal among the six strains of the mice tested. Key words: Mouse strain, Clonorchis sinensis, egg-laying capacity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.10
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• pp.1855-1861
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• 2017

In this paper, the gain enhancement of an SDPA using a director and two parasitic patches is studied. The modified balun is used to increase the bandwidth, whereas the director and two parasitic patches are appended to the SDPA to enhance the gain in the middle and high frequency bands. The effects of the distance between the director and parasitic patches on the antenna performance are analyzed, and the SDPA with a gain over 7 dBi at 1.54-2.99 GHz band is designed. The proposed SDPA is fabricated on an FR4 substrate with a dimension of $90mm(L){\times}135mm(W)$ in order to validate its performance. The fabricated antenna shows a frequency band of 1.56-3.10 GHz for a VSWR < 2, and it is confirmed by measurement that gain maintains over 7 dBi in the frequency range of 1.54-3.00 GHz.

• 건강소식
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• v.6 no.7 s.45
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• pp.27-30
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• 1982

• Journal of the Microelectronics and Packaging Society
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• v.31 no.3
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• pp.99-104
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• 2024

With the advancement of power electronics technology and the increasing demand for high-efficiency power semiconductors, silicon carbide (SiC) devices have gained attention as an alternative to overcome the limitations of traditional silicon (Si) semiconductors. SiC devices enable excellent switching efficiency due to their high switching speed. However, parasitic inductance within the power module can cause voltage oscillations and overshoot phenomena, potentially leading to issues with electrical reliability and efficiency. To address these challenges, two approaches were proposed and validated. The first approach involved applying an RC snubber circuit to mitigate the effects of parasitic inductance, thereby improving electrical stability. The second approach focused on optimizing the lead-frame design to reduce parasitic inductance. Both methods were verified through simulations and experiments, demonstrating that the electrical reliability and efficiency of SiC power modules can be simultaneously improved.