• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.25-31
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• 2016

Parasitic capacitance and resistance of FinFET transistors are the important components that determine the frequency performance of the circuit. Therefore, the researchers in our group developed more accurate parasitic capacitance and resistance for FinFETs than BSIM-CMG. To verify the RF performance, proposed model was applied to design an LNA that has $S_{21}$ more than 10dB and center frequency more than 60GHz using HSPICE. To verify the accuracy of the proposed model, mixed-mode capability of 3D TCAD simulator Sentaurus was used. $S_{21}$ of LNA was chosen as a reference to estimate the error. $S_{21}$ of proposed model showed 87.5% accuracy compared to that of Sentaurus in 10GHz~100GHz frequency range. The $S_{21}$ accuracy of BSIM-CMG model was 56.5%, so by using the proposed model, the accuracy of the circuit simulator improved by 31%. This results validates the accuracy of the proposed model in RF domain and show that the accuracies of the parasitic capacitance and resistance are critical in accurately predicting the LNA performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.3 s.357
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• pp.78-84
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• 2007

A multistandard direct-conversion mixer for WCDMA, Wibro, and 802.11a/b/g is designed in 0.18 um CMOS technology To support multistandard and to reduce the chip area the switched inductor is used as the matching method. This switched inductor matching network selects the mixer's operation frequency band by turning on or off the switch transistor. Since the performances of mixer and operation frequency can be affected by the parasitic of switch transistor the mixer should be designed with the optimized size of switch to minimize parasitic effects. Proposed mixer is able to achieve return loss less than -13 dB in $2.1\sim2.5GHz$ and $5.1\sim5.9GHz$ bands with the suitable performance to meet requirements of WCDMA, WiBro, and 802.11a/b/g.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.239-241
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• 2006

본 논문에서는 Liquid crystal display (LCD) Backlight module중에 Cold cathode fluorescent lamp (CCFL)를 포함한 인버터가 가지고 있는 기생 용량 측정 방법을 고안하였다. CCFL의 부성 저항 특성을 고려하여 램프의 정적 저항 성분을 일정하게 유지시키고 입력 전압 대 출력 전압의 비 중 최대 Gain을 갖는 주파수를 찾아내 기생 용량을 계산하는 Algorithm을 완성하였다. 시뮬레이션과 실험 결과를 통해 비교 검증함으로써 측정 방법의 유효성을 입증하였다.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.156-157
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• 2012

최근 국내에서도 다양한 형태의 전력반도체 모듈이 개발되고 있으며 대용량화에 따라 전력반도체 패키지 내부에 소자의 병렬연결이 흔히 사용되고 있다. 이에 따라 회로의 구조에 따른 기생 임피던스, 즉, 인덕턴스와 저항 성분은 개별 소자의 안전영역(SOA)을 넘는 스트레스를 발생시키고 고장을 일으킬 수 있다. 이러한 기생 임피던스를 모듈 설계 단계에서 시뮬레이션을 통해 분석하여 이에 의한 영향을 예측하고 설계에 반영하여 고 신뢰성 차량용 전력반도체 모듈을 개발하고자 한다.

• Korean journal of applied entomology
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• v.41 no.2
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• pp.99-105
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• 2002

A gregarious pupal endoparasitoid Tetrastichsus sp. (Hymenoptera: Eulophidae) was reared in vitro from oviposition to adult emergence on an artificial host. The host pupal case was made using 0.02 mm-thick polypropylene film, and was filled with a diet consisting of powders of Antheraea pernyi pupa, chicken yolk, infant formula, royal jelly, and Neisenheimer's salt solution. Female parasitoids reared in the artificial host produced smaller sized progeny than those reared in in vivo, but the adults reproduced fertile offsprings. Furthermore in vitro second-generation (G$_2$) females showed more improved biological characteristics, compared with their parents. The fecundity (mean no. adult progeny), oviposition period (days), and longevity (days) of G$_2$ female were evaluated as 45.7, 7.8, and 13.8, respectively Female biased sex ratio was obtained with 76.9% female progeny. The results demonstrated that Tetrastichus sp. is a promising parasitoid for in vitro mass production.

• Journal of IKEEE
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• v.24 no.3
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• pp.845-852
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• 2020

Developing standard cells for 3nm and beyond requires significant advances in the device and interconnect technology. Thus, it is very important to quantify the impact of the new technology in various aspects. In this paper, we perform a through analysis on the impact of Buried Power Rail (BPR) and Complementary FET (CFET) in the perspective of cell area and parasitics such as capacitance. We emphasize that CFET is a technology that realizes 4T and beyond for standard cell designs, but significant capacitance increases (+18.0%), compared to its counterpart technology (FinFET) cell, due to the increase of cell height in the Z-direction.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.11-18
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• 1997

By utilizing the technique to monitor the DC cell node voltages through circuit simulation, degradation of the static read operating margin In high load-resistor SRAM cell was examined, which is caused by parasitic resistances and transistor asymmetries in this cell structure. By selectively adding the parasitic resistances to an ideal cell, the influence of each parasitic resistance on the operating margin was examined, and then the cases with parasitic resistances in pairs were also examined. By selectively changing the channel width of cell transistors to generate cell asymmetry, the influence of cell asymmetry on the operating margin was also examined. Analyses on the operating margins were performed by comparing the supply voltage values at which two cell node voltages merge to a single value and the differences of cell node voltages at VDD=5V in the simulated node voltage characteristics. By determining the parasitic resistances and the transistor asymmetries which give the most serious effect on the static read-operation of SRAM cell from this analysis based on circuit simulated, a criteria was provided, which can be referred in the design of new SRAM cell structures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.11-116
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• 2000

A topology decreased switching loss and voltage stress by zero voltage switching is presented in this paper. Generally, Switching mode converting productes voltage stress and power losses due to excessive voltage and current. which affect to performance of power supply and reduce overall efficiency of equipments. Virtually, In flyback converter, transient peak voltage and current at switcher are generated by parasitic elements. To solve these problems, present ZVS flyback converter topology applied a auxiliary circuit. Incorporation of auxiliary circuit into a conventional flyback topology serves to reduce power losses and to minimize switching voltage stress. Snubber capacitor in auxiliary circuit serves ZVS state by control voltage variable time at turn on and off of main switch, then reduces voltage stress and power losses. The proposed converter has lossless switching in variable load condition with wide range. A detailed analysis of the circuit is presented and the operation procedure is illustrated. A (50W 100kHz prototype) ZVS flyback converter using a auxiliary circuit is built which shows an efficiency improvement as compared to a conventional hard switching flyback converter.