• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.57-63
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• 2014

This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.1-11
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• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1311-1319
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• 1998

The methods of providing available bandwidth adaptively using feedback to maximize the utilization of network as well as the quality of service have been the focus of recent research activities for ATM(Asynchronous Transfer Mode). This study has been extended from the point-to-point connection to a point-to-multipoint environment as the number of applications requiring multicast service increases. It is known that the effectiveness of feedback based congestion control scheme diminishes as propagation delay increases. Especially for a multicast connection consisting of various paths and destinations with different performance and congestion status, the problem of unfairness due to different propagation delays may occur. The degree of such unfairness may change depending on various aspects of congestion control schemes. These has been, however, relatively little study on these problems. In this paper, we present how various aspects of control schemes-length of the interval between feedback generations, point of time to coalesce feedback cells from child paths, decreasing factor of source rate in case of congestion-affect the degree of unfairness. Simulation results show that degree of unfairness changes according to when the feedback coalescing happens. Expecially it is shown that the effect of feedback coalescing time to the degree of unfairness is more significant for the smaller feedback interval. It is also found that as the source rate decreasing factor becomes larger the average ACR(Allowed Cell Rate) at the source gets lower and the degree of unfairness grow larger.

• Journal of Life Science
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• v.14 no.1
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• pp.131-140
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• 2004

T7 bacteriophage gp4 is the replicative DNA helicase that unwinds double-stranded DNA by utilizing dTTP hydrolysis energy. The quaternary structure of the active form of T7 helicase is a hexameric ring with a central channel. Single-stranded DNA passes through the central channel of the hexameric ring as the helicase translocates $5'\rightarrow3'$ along the single-stranded DNA. The DNA unwinding was measured by rapid kinetic methods and showed a lag before the single-stranded DNA started to accumulate exponentially. This behavior was analyzed by a kinetic stepping model for the unwinding process. The observed lag phase increased as predicted by the model with increasing double-stranded DNA length. Trap DNA added in the reaction had no effect on the amplitudes of double-stranded DNA unwound, indicating that the $\tau7$ helicase is a highly processive helicase. Global fitting of the kinetic data to the stepping model provided a kinetic step size of 10-11 bp/step with a rate of $3.7 s^{-1}$ per step. Both the mechanism of DNA unwinding and dTTP hydrolysis and the coupling between the two are unaffected by temperature from $4∼37^{\circ}C$. Thus, the kinetic stepping for dsDNA unwinding is an inherent property of tile replicative DNA helicase.

• Polymer(Korea)
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• v.39 no.2
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• pp.317-322
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• 2015

Salinity gradient power is a system which sustainably generates electricity for 24 hrs, if the system is constructed at a certain place where both seawater and river water are consistently pumped. Since power is critically determined by the water flux and the salt rejection, a membrane of water-semipermeable aquaporin protein in cell membranes was studied for pressure-retarded osmosis. NaCl was used as a salt, and $NaNO_3$ was used as a candidate to check the ion selectivity. The water flux of biomimetic aquaporin membranes was negligible at a concentration below 2M. Also, there is no remarkable dependence of water flux and ion selectivity on concentrations higher than 3M. Therefore, the biomimetic aquaporin membrane could not be applied into pressure-retarded osmosis; however, if a membrane could overcome the current limitations, the properties shown by natural cells could be accomplished.

• Journal of the Korea Society for Simulation
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• v.33 no.2
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• pp.1-11
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• 2024

A cyber-physical system is a technology that connects the physical systems of a manufacturing environment with a cyber space to enable simulation. One of the major challenges in this technology is the seamless communication between these two environments. In complex manufacturing processes, it is crucial to adapt to various protocols of manufacturing equipment and ensure the transmission and reception of a large volume of data without delays or errors. In this study, we propose a method for constructing agent models for real-time simulation-capable cyberphysical systems. To achieve this, we design data collection units as independent agent models and effectively integrate them with existing simulation tools to develop the overall system architecture. To validate the proposed structure and ensure reliability, we conducted empirical testing by integrating various equipment from a real-world smart microfactory system to assess the data collection capabilities. The experiments involved testing data delay and data gaps related to data collection cycles. As a result, the proposed approach demonstrates flexibility by enabling the application of various internal data collection methods and accommodating different data formats and communication protocols for various equipment with relatively low communication delays. Consequently, it is expected that this approach will promote innovation in the manufacturing industry, enhance production line efficiency, and contribute to cost savings in maintenance.

• Korean Journal of Food Science and Technology
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• v.42 no.4
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• pp.494-501
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• 2010

The purpose of this study was to examine the presence of Bacillus cereus, aerobic bacteria and coliforms in the raw material of infant formulas and investigate the manufacturing process in terms of microbial safety. Among ten kinds of raw infant formula material samples (n=20), Bacillus cereus appeared in two (n=4). Aerobic bacteria were not detected in raw infant formula material or maximum 4.15 log CFU/g. Eleven species of aerobic bacteria were isolated and 76% of them were Sphingomonas paucimobilis, Pseudomonas fluorescens, Rhizobium radiobactor, or Stenotrophomonas maltophilia. A Pearson's correlation analysis revealed that the most influential factors for detecting Bacillus cereus were aerobic bacteria and coliforms. In other words, when the measured values of aerobic bacteria and coliforms were higher, the possibility that Bacillus cereus would appear increased. In a regression model to predict Bacillus cereus, the rate of appearance was correlated with aerobic bacteria and coliforms, and its contribution rate for effectiveness was 86%. Improving microbial quality control by pasteurization, spray dry, popping and extrusion resulted in a decrease in the numbers of Bacillus cereus, aerobic bacteria and coliforms in the raw materials. The results suggest that a hazard analysis and critical control point system might be effective for reducing microbiological contamination.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.51-54
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• 2008

PON(Passive Optical Network) is the promising technology applicable to TPS(Triple Play Service). To improve process the packet, MAC(Multiple Access Control) is the most important technology in the PON. The core of MAC is DBA(Dynamic Bandwidth Assignment), it classifies SR-DBA(Status Report DBA) and NSR-DBA(Non Status Report DBA). But GPON DBA is using BPON's DBA, so it's bad in network efficiency. This study develop BR(Borrow-Refund)-DBA for improve network efficiency and prompt process. For take the gauge of performance evaluation, estimate about throughput, fairness and queue delay in SR-DBA and NSR-DBA environment

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2002.04a
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• pp.67-75
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• 2002

Digital photogrammetry is one of the powerful tools for surveying in more perceptual ways and exploiting the continuously developing computer technology. Nowadays, digital photogrammetry is being used for a number of industrial measurements and inspections but the automation aspect of this technique is not fully developed yet. Photogrammetric work, which is obtained through usual workflow, delays for a big amount of CGP surveying, interpretation and cadastral information. Therefore through studying ways of reducing the volume of photogrammetric works, financial opportunities for digital photogrammetry can be found. This research is focused on the development of the new workflow and study algorithm in digital photogrammetry. Using this result we can reduce financial expenses and improve technologies of topographic and cadastral plans creation.