• Education of Primary School Mathematics
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• v.22 no.1
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• pp.65-82
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• 2019

In this study, students' multiplication expression method according to visual model was analyzed through paper test and eye tracking test. As a result of the paper-pencil test, students were presented with multiplication formula. In the group model (number of individual pieces in a group) ${\times}$ (number of group) in the array model (column) ${\times}$ (row), but in the array model, the proportion of students who answered the multiplication formula in the (row) ${\times}$ (column). From these results, we derived the appropriate model presentation method for multiplication instruction and the multiplication expression method for visual model.

• Communications of Mathematical Education
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• v.18 no.1 s.18
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• pp.73-87
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• 2004

현장에서 수업을 하다 보면 의외로 학생들이 곱셈구구는 잘 외우고 있지만 곱셈의 개념에 대해서는 잘 모르고 있다는 것을 많이 발견할 수 있다. 이것은 곱셈에 대한 개념을 도입할 때 학생들이 왜 곱셈을 배우는가에 대해서 스스로 절실하게 생각해 보고 발견해 보는 경험이 부족했기 때문이라고 생각한다. 곱셈이 왜 필요하고 곱셈식으로 나타내는 것이 얼마나 좋은 방법인지 학생들이 깨달아 덧셈구조에서 곱셈구조로의 개념의 변화가 일어날 수 있도록 지도한다면 이러한 문제점을 어느 정도 해결할 수 있지 않을까 생각해본다. 따라서, 본 연구에서는 자연수의 곱셈에 대한 이론적 배경과 교육과정을 알고 이를 바탕으로 수학교육 이론에 근거한 자연수의 곱셈의 교수-학습 지도 방안에 대하여 거시적 입장에서 고찰해 보고자 한다.

• Journal of Educational Research in Mathematics
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• v.27 no.2
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• pp.249-267
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• 2017

The unit of multiplication in the mathematics textbook for third graders deals with two-digit number multiplied by one-digit number. Students tend to perform multiplication without necessarily understanding the principle behind the calculation. Against this background, we designed the unit in a way for students to explore the principle of multiplication with cuisenaire rods and array models. The results of this study showed that most students were able to represent the process of multiplication with both cuisenaire rods and array models and to connect such a process with multiplicative expressions. More importantly, the associative property of multiplication and the distributive property of multiplication over addition were meaningfully used in the process of writing expressions. To be sure, some students at first had difficulties in representing the process of multiplication but overcame such difficulties through the whole-class discussion. This study is expected to suggest implications for how to teach multiplication on the basis of the properties of the operation with appropriate instructional tools.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1092-1097
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1256-1261
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.37-39
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• 2001

본 논문은 여러 가지 데이터 압축 표준에서 채택하고 있는 이차원 이산 여현 변환과 그 역 변환 (DCT/IDCT)를 위한 효율적인 비동기식 행렬 벡터 곱셈기를 설계하였다. 본 논문에서 제안되어진 곱셈기는 일반적으로 DCT/IDCT의 입력 데이터가 대부분 zero입력이거나 또는 작은 비트수로 표현 가능하다는 점을 이용하여 저전력 고성능 동작을 구현할 수 있도록 설계하였다. 비동기식 설계 방식을 채택하여 Zero입력일 경우 곱셈과정을 생략하고, 정적 회로에 기초한 특정 계산 완료 인지 방식(Speculative Completion Sensing)와 비트 분할된 곱셈기를 이용하여 입력 비트 슬라이스에 대해 동적으로 회로의 계산부분을 활성화/비활성화를 동작을 할 수 있도록 설계되어졌다.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Education of Primary School Mathematics
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• v.25 no.1
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• pp.57-79
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• 2022

Current mathematics It is necessary to ensure that ratio and proportion concept is not distorted or broken while being treated as if they were easy to teach and learn in school. Therefore, the purpose of this study is to analyze the activities presented in the textbook. Based on prior work, this study reinterpreted the proportional reasoning task from the proportional perspective of Beckmann and Izsak(2015) to the multiplicative structure of Vergnaud(1996) in four ways. This compared how they interpreted the multiplicative structure and relationships between two measurement spaces of ratio and rate units and proportional expression and proportional distribution units presented in the revised textbooks of 2007, 2009, and 2015 curriculum. First, the study found that the proportional reasoning task presented in the ratio and rate section varied by increasing both the ratio structure type and the proportional reasoning activity during the 2009 curriculum, but simplified the content by decreasing both the percentage structure type and the proportional reasoning activity. In addition, during the 2015 curriculum, the content was simplified by decreasing both the type of multiplicative structure of ratio and rate and the type of proportional reasoning, but both the type of multiplicative structure of percentage and the content varied. Second, the study found that, the proportional reasoning task presented in the proportional expression and proportional distribute sections was similar to the previous one, as both the type of multiplicative structure and the type of proportional reasoning strategy increased during the 2009 curriculum. In addition, during the 2015 curriculum, both the type of multiplicative structure and the activity of proportional reasoning increased, but the proportional distribution were similar to the previous one as there was no significant change in the type of multiplicative structure and proportional reasoning. Therefore, teachers need to make efforts to analyze the multiplicative structure and proportional reasoning strategies of the activities presented in the textbook and reconstruct them according to the concepts to teach them so that students can experience proportional reasoning in various situations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.