• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.309-324
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• 1987

In recent years has been an increasing interest with respect to using the discrete cosine transform(DCT) of which performance is found close to that of the Karhumen-Loeve transform, known to be optimal in the area of digital image processing for tha purpose of the image data compression. Among most of reported algorithms aimed at lowering the coputation complexity. Chen's algorithm is is found to be most popular, Recently, Lee proposed a now algorithm of which the computational complexity is lower than that of Chen's. but its performance is significantly degraded by FWL(Finite-Word-Lenght) effects as a result of employinga a fixed-poing arithmetic. In this paper performance evaluation of these two algorithms and error analysis of FWL effect are described. Also a scaling technique which we call Up & Down-scaling is proposed to allevaiate a performance degradation due to fixed-point arithmetic. When the 16x16point 2DCT is applied on image data and a 16-bit fixed-point arithmetic is employed, both the analysis and simulation show that is colse to that of Chen's.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.489-492
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• 2000

본 논문에서는 영상 항법 변수 추출 알고리듬의 실시간 구현에 관해 연구하였다. 영상 항법 변수 추출 알고리듬은 이전 위치를 기준으로 현재 위치를 추정해내는 상대위치 추정 알고리듬과 상대위치 추정에 의해 누적되는 오차를 보정하기 위한 절대위치 보정 알고리듬으로 구성된다. 절대위치 보정 알고리듬은 고해상도 영상과 IRS (Indian Remote Sensing) 위성영상을 기준영상으로 이용하는 방법 및 DEM (Digital Elevation Model) 을 이용하는 방법으로 구성된다. 하이브리드 영상 항법 변수 추출 알고리듬을 실시간으로 구현하기 위해 MVP (Multimedia Video Processor)로 명명된 TMS320C80 DSP (Digital Signal Processor) 칩을 사용하였다. 구현된 시스템은 MVP의 부동 소수점 프로세서인 MP (Master Processor) 를 고정 소수점 프로세서인 PP (Parallel Processor) 를 제어하거나 삼각함수 계산과 같은 부동 소수점 함수를 계산하는데 사용하였고, 대부분의 연산은 PP를 사용하여 수행하였다. 처리시간이 많이 필요한 모듈에 대해서는 고속 알고리듬을 개발하였고, 4개의 PP를 효율적으로 사용하기 위한 영상분할 방법에 대해 제안하였다. 비행체에서 캡코더를 이용해 촬영한 연속 항공 영상과 비행체의 자세정보를 입력으로 실시간 시뮬레이션 하였다. 실험결과는 하이브리드 항법 변수 추출 알고리듬의 실시간 구현이 효과적으로 구현되었음을 나타내고 있다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.2
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• pp.37-43
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• 2009

In this study, multi-channel digital hearing aid algorithm for low power system is proposed. First, MDCT(Modified Discrete Cosine Transform) method converts time domain of input speech signal into frequency domain of it. Output signal from MDCT makes a group about each channel, and then each channel signal adjusts a gain using LCF(Loudness Compensation Function) table depending on hearing loss of an auditory person. Finally, compensation signal is composed by TDAC and IMDCT. Its all of process make progress 16-bit fixed-point operation. We use fast-MDCT instead of MDCT for reducing system complexity and previously computed tables instead of log computation for estimating a gain. This algorithm evaluate through computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.4
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• pp.65-71
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• 2000

Finite wordlength effect of the recursive implementation of SDFT(sliding-DFT) is analytically derived in this paper. Representation errors of the twiddle coefficients and the data registers are the two major causes of the spectral errors in the recursive implementation. The noise-to-signal ratio is analytically derived in terms of the coefficients wordlength, the data registers wordlength, and the DFT's block-length used in the computation Error dynamic equation is obtained from the recursive DFT and the probabilistic models for the coefficients error and the round-off error are introduced for the NSR derivation, The result of the NSR derivation is verified with the simulation data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.371-373
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• 2015

This paper describes an analysis of hardware design conditions of moving object detection algorithm which is based on effective Gaussian mixture learning (EGML). The simulation model of EGML algorithm is implemented using OpenCV, and it is analyzed that the effects of parameter values on background learning time and moving object detection sensitivity for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-width parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.6
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• pp.526-534
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• 1990

In the implementation of digital filters, the coefficient errors are occurred when filter coefficients are quantized by finite wordlength. They change the frequency responsed and output characteristics of the filters and therefore they become a main reason which could stimulate coefficient sensitivity especially in recursive filters. In this paper, we study the characteristics of coefficient sensitivity for WDF that is less effective to the coefficient errors. The simulation based on the method of fixed-point quantization demonstrates that the frequency responses of WDF have better preformance than those of conventional cascade IIR filter when variations of finite wordlength is considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.85-100
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• 1991

In the discussion of digital mobile communication systems the speech coder based on the high quality low bit rate is an essential part of topics to overcome the limited availability of radio spectrum, which will enhance the communication services. In this paper we present the implementation and performance evaluation of 13kbps RPE LTP speech coder. An implementation of a real time full duplex coder with 75% of DSP loading rate using a single DSP chip has been shown, and also the fixed point simulations for H/W implementation has been performed. Finally, analysis result for relative bit importance of each transmitting parameter has been shown for channel coding.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.4
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• pp.173-179
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• 2002

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. The DFE structure has better channel adaptive performance and lower BER than the transversal structure. The proposed equalizer can be used for 16/64 QAM modems. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL filter. The proposed equalizer shows low BER in multipath fading channel. We have performed models. From the simulation results, we employ a 12 tap feedback filter and a 8 tap feedforward logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5$\mu\textrm{m}$ standard cell library (STD80) and verified function and timing simulations. The total number of gates is about 130,000.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.