• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.439-444
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• 2005

We investigated the structural and electrical properties of BLT films grown on Si covered with $ZrO_{2}$ buffer layer. The BLT thin film and $ZrO_{2}$ buffer layer were fabricated using a metalorganic decomposition method. The electrical properties of the MFIS structure were investigated by varying thickness of the $ZrO_{2}$ layer. AES and TEM show no interdiffusion and reaction that suppressed using the $ZrO_{2}$ film as a buffer layer The width of the memory window in the C-V curves for the MFIS structure decreased with increasing thickness of the $ZrO_{2}$ layer. It is considered that the memory window width of MFIS is not affected by remanent polarization. Leakage current density decreased by about four orders of magnitude after using $ZrO_{2}$ buffer layer. The results show that the $ZrO_{2}$ buffer layers are prospective candidates for applications in MFIS-FET memory devices.

• 한국세라믹학회지
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• 제42권9호
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• pp.624-630
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• 2005

To investigate the possibility of the $ZrO_2$ buffer layer as the insulator for the Metal-Ferroelectric-Insulator-semiconductor (MFIS) structure, $ZrO_2$ and $SrBi_2Ta_2O_9$ (SBT) thin films were deposited on the P-type Si(111) wafer by the R.F. magnetron-sputtering method. According to the process with and without the post-annealing of the $ZrO_2$ buffer layer and SBT thin film, the diffusion amount of Sr, Bi, Ta elements show slight difference through the Glow Discharge Spectrometer (GDS) analysis. From X-ray Photoelectron Spectroscopy (XPS) results, we could confirm that the post-annealing process affects the chemical binding condition of the interface between the $ZrO_2$ thin film and the Si substrate. Compared to the MFIS structure without the post-annealing of the $ZrO_2$ buffer layer, memory window value of MFlS structure with post-annealing of the $ZrO_2$ buffer layer were considerably improved. The window memory of the Pt/SBT (260 nm, $800^{\circ}C)/ZrO_2$ (20 nm) structure increases from 0.75 to 2.2 V under the applied voltage of 9 V after post-annealing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국세라믹학회지
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• 제42권2호
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• pp.104-109
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• 2005

PbO 완충층의 역할을 확인하기 위해, r.f. magnetron sputtering법을 이용하여 p-type (100) Si 기판 위에 $Pt/Pb_{1.1}Zr_{0.53}Ti_{0.47}O_{3}$와 PbO target으로 Pt/PZT/PbO/Si의 MFIS 구조를 제조하였다. MFIS 구조에 완충층으로 PbO를 삽입함으로써 PZT 박막의 결정성이 크게 향상되었고, 박막의 공정온도도 상당히 낮출 수 있었다. 그리고 XPS depth profile 분석 결과, PbO 증착시 기판온도가 PbO와 Si의 계면에서 Pb의 확산에 미치는 영향을 확인하였다. PbO 완충층을 삽입한 MFIS는 높은 메모리 윈도우와 낮은 누설전류 밀도를 가지는 추수한 전기적 특성을 나타내었다. 특히, 기판온도 $300^{\circ}C$에서 증착된 PbO를 삽입한 Pt/PZT(200nm, $400^{\circ}C)PbO(80nm)/Si$는 9V의 인가전압에서 2.OV의 가장 높은 메모리 윈도우 값을 나타내었다.

• 한국초전도ㆍ저온공학회논문지
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• 제6권3호
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• pp.12-15
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• 2004

There are two major approaches to obtain texture template for HTS coated conductor (CC) ---IBAD and RABiTS. CC's with IBAD template showed both longer and higher Ic results so far. IBAD for CC began with YSZ, the processing of which is very slow compared to other processings needed for the fabrication of CC. Because of this very slow processing speed, IBAD with other materials such as Gd$_2$Zr$_2$O$_{7}$(GZO) and MgO have been developed. The processings of IBAD-GZO and IBAD-MgO are known to be up to 3times and 100 times. respectively, as fast as the processing of IBAD-YSZ. IBAD-MgO is very attractive in that the processing is very fast. IBAD-MgO also needs additional buffer layer(s). Many materials are being investigated to be used as a buffer layer on top of the MgO. BaZrO$_3$ (BZO) is a good candidate as the buffer layer on top of the IBAD-MgO because it is chemically stable and does not react with YBCO at high temperatures. It also has good lattice match with MgO. The BZO film has been deposited on single crystal MgO, and YBCO film was deposited on BZO/MgO to investigate the possibility of using BZO as both the buffer and capping layer of the CC.C.

• 한국세라믹학회지
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• 제40권1호
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• pp.52-61
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• 2003

R.F 마그네트론 스퍼터링법으로 ZrO$_2$ 확산 방지막과 SrBi$_2$Ta$_2$$O_{9}$ 강유전 박막을 증착하여 MFIS 구조론 제작하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해서 일반 분리기로와 RTA로에서 각각 산소 분위기와 아르곤 분위기에서 550~85$0^{\circ}C$의 온도범위에서 후열처리를 행한 후, C-V 특성 및 누설전류 특성을 분석하였다. RTA 75$0^{\circ}C$ 산소 분위기에서 후열처리된 20nm의 두께를 가지는 ZrO$_2$ 박막에서 최대의 메모리 윈도우 값을 얻었다. Pt/SBT(260nm)ZrO$_2$(20nm)/Si 구조는 Pt/SBT(260nm)/Si 구조의 값보다 C-V 특성 및 누설전류 특성이 우수하였으며 이러한 결과는 ZrO$_2$ 박막이 SBT와 Si사이에서 우수한 완충층의 역할을 함을 알 수 있었다.

• 한국초전도ㆍ저온공학회논문지
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• 제10권3호
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• pp.5-8
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• 2008

On highly-textured IBAD-MgO templates, we have tried to find proper buffer layers among various candidate materials, including $LaMnO_3$ (LMO), $La_2Zr_2O_7$ (LAO), $LaAlO_3$ (LAO), $LaGaO_3$ (LGO), $NdGaO_3$ (NGO), and $BaZrO_3$ (BZO). All buffer layers were deposited on the IBAD-MgO templates by KrF pulsed laser deposition(PLD). LAO layer showed an armorphous phase. LZO, LGO, and NGO layers showed polycrystalline growth. Only LMO and BZO layers exhibited c-axis oriented biaxially textured films. Optimally processed LMO buffer layer at deposition temperature of $750^{\circ}C$ and $PO_2$ of 100mTorr exhibited ${\triangle}{\phi}$ value of ${\sim}-5.2^{\circ}$ and RMS roughness of 5.6nm. Interestingly, BZO buffer layers with ${\triangle}{\phi}$ values of ${\sim}-6^{\circ}$ could be routinely produced over a wide PLD processing condition.

• 한국자기학회지
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• 제9권6호
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• pp.306-311
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• 1999

Water-based sol-gel 법으로 La2/3Sr1/3MnO3(LSMO)/YSZ/SiO2/Si(100) 다결정체 박막을 제조하여 YSZ 중간층 도입에 따른 상온, 120 Oe의 저 자장영역에서 측정한 tunnel-type 자기저항 변화에 미치는 영향에 대하여 고찰하였다. 페롭스카이트 단일상을 갖는 미세한 LSMO 박막을 얻을 수 있었으며, YSZ 중간층을 도입하지 않은 박막의 자기저항 변화비는 최대 약 0.20%이었으나, YSZ 중간층을 도입한 경우 자기저항비가 0.42%로 증가하였다. 이러한 tunnel-type 자기저항의 증가 현상은 YSZ 중간층이 SiO2/Si(100) 기판과 La2/3Sr1/3MnO. 자성박막 사이에서 확산 장벽층으로서의 역할을 수행하여 LSMO 박막의 미세구조 특성 향상 및 확산반응에 의하여 생성된 dead layer를 감소시켜 나타난 결과이다.

• 한국세라믹학회지
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• 제39권4호
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• pp.377-385
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• 2002

Metal-Ferroelectric-Insulator-Semiconductor(MFIS) 구조의 적용하기 위해 R. F. 마그네트론 스퍼터를 이용하여 p-type Si(111) 기판 위에 $ZrO_2$와 $SrBi_2Ta_2O_9$ 박막을 증착하였다. SBT 박막은 $ZrO_2$ 완충층을 삽입함으로써 MFIS 구조의 전기적인 특성이 향상되었다. $ZrO_2$ 박막의 두께를 고정하고 SBT 박막의 두께를 160nm에서 220nm으로 변화시키면서 윈도우 메모리를 3-9V의 범위에서 측정하였다. Pt/SBT(160nm)/$ZrO_2$(20nm)/Si의 조건에서 최대 2.2V 메모리 윈도우 값을 얻을 수 있었으며 이 메모리 윈도우 값은 실제 적용되는 저전압 NDRO-FRAM 구동에 충분한 값이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1240_1241
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• 2009

In this paper, sol-gel-spin coated $Pb(ZrTi)O_3$ thin film with $ZrO_2$ buffer-layer and $PbTiO_3$ seed-layer was investigated for vibration MEMS energy harvester to scavenge power from ambient vibration via d33 piezoelectric mode. Piezoelectric thin film deposition techniques on insulating layer is the important key for $d_{33}$ mode of piezoelectric vibration energy harvester. $ZrO_2$ buff-layer was utilized as an insulating layer. $PbTIO_3$ seed-layer was applied as an inter-layer between PZT and $ZrO_2$ layer to improve the crystalline of PZT thin film. The fabricated PZT thin film had a remanent polarization of 5.3uC/$cm^2$ and the coercive field of 60kV/cm. The fabricated energy harvester using PZT thin film with PTO seed-layer generated 1.1uW of electrical power to $2.2M{\Omega}$ of load with $4.4V_{pvp}$ from vibration of 0.39g at 528Hz.