• Title/Summary/Keyword: worst-case analysis

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Timing Verification of AUTOSAR-compliant Diesel Engine Management System Using Measurement-based Worst-case Execution Time Analysis (측정기반 최악실행시간 분석 기법을 이용한 AUTOSAR 호환 승용디젤엔진제어기의 실시간 성능 검증에 관한 연구)

  • Park, Inseok;Kang, Eunhwan;Chung, Jaesung;Sohn, Jeongwon;Sunwoo, Myoungho;Lee, Kangseok;Lee, Wootaik;Youn, Jeamyoung;Won, Donghoon
    • Transactions of the Korean Society of Automotive Engineers
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    • v.22 no.5
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    • pp.91-101
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    • 2014
  • In this study, we presented a timing verification method for a passenger car diesel engine management system (EMS) using measurement-based worst-case execution time (WCET) analysis. In order to cope with AUTOSAR-compliant software architecture, a development process model is proposed. In the process model, a runnable is regarded as a test unit and its temporal behavior (i.e. maximum observed execution time, MOET) is obtained along with on-target functionality evaluation results during online unit test. Furthermore, a cost-effective framework for online unit test is proposed. Because the runtime environment layer and the standard calibration environment are utilized to implement test interface, additional resource consumption of the target processor is minimized. Using the proposed development process model and unit test framework, the MOETs of 86 runnables for diesel EMS are obtained with 213 unit test cases. Using the obtained MOETs of runnables, the WCETs of tasks are estimated and the schedulability is evaluated. From the schedulability analysis results, the problems of the initially designed schedule table is recognized and it is fixed by redesigning of the runnable mapping and task offset. Through the various test scenarios, the proposed method is validated.

Performance Analysis of UWB Systems in the Presence of Timing Jitter

  • Guvenc, Ismail;Arslan, Huseyin
    • Journal of Communications and Networks
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    • v.6 no.2
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    • pp.182-191
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    • 2004
  • In this paper, performances of different ultra-wideband (UWB) modulation schemes in the presence of timing jitter are evaluated and compared. Static and Rayleigh fading channels are considered. For fading channels, Oat and dispersive channels are assumed. First, bit error rate (BER) performances for each case are derived for a fixed value of timing jitter. Later, a uniform distribution of jitter is assumed to evaluate the performance of the system, and the theoretical results are verified by computer simulations. Finger estimation error is treated as timing jitter and an appropriate model is generated. Furthermore, a worst case distribution that provides an upper bound on the system performance is presented and compared with other distributions. Effects of timing jitter on systems employing different pulse shapes are analyzed to show the dependency of UWB performance on pulse shape. Although our analysis assumes uniform timing jitter, our framework can be used to evaluate the BER performance for any given probability distribution function of the jitter.

A Low Phase Noise Design of Voltage Controlled Dielectric Resonator Oscillator and Reliability Analysis (전압제어 유전체 공진 발진기의 저위상잡음 설계 및 신뢰도 분석)

  • Ryu Keun-Kwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.2
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    • pp.408-414
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    • 2005
  • The VCDRO(Voltage Controlled Dielectric Resonate. Oscillator) with low phase noise is designed using nonlinear analysis, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise performance, and the quality factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCDRO and the reliability analysis is accomplished to estimate the probability of operation at the end of life. The developed VCDRO has the oscillating tuning factor of 0.56MHZ1V for the control voltage range of 0-l2V. This VCDRO requires the DC power of 136mW. The phase noise characteristics exhibit good performances of -94.18dBc/Hz (a)10KHz and -116.3dBc/Hz (a)100KHz. And, the output power over 7.33dBm is measured.

A Study on Compatibility between DTV and CDMA System (DTV와 CDMA 시스템간의 양립성 분석에 관한 연구)

  • Cheng, Yan-Ming;Lee, Il-Kyoo;Shim, Yong-Sup;Kim, Jong-Tae;Lee, Kyoung-Kun
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.10 no.3
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    • pp.75-82
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    • 2010
  • Korea has made a plan to allocate CH 14~CH 51 (470 MHz~698 MHz) for DTV. This paper assumes that DTV operates on CH 51 (692 MHz~698 MHz) and CDMA system operates on CH 52 (698 MHz~704 MHz) in spare band. Minimum Coupling Loss (MCL) method to get protection distance and Spectrum Engineering Advanced Monte Carlo Analysis Tool (SEAMCAT) to get guard band through 5 % interference probability are used. The protection distance is required to be 665.67 km at close frequency offset of 698.625 MHz between DTV transmitter and CDMA Base Station (BS) receiver. The required guard band between DTV transmitter and CDMA Mobile Station (MS) receiver is 5 MHz for the worst case of rural environment. There is no serious impact between CDMA MS transmitter and DTV receiver. The required guard band between CDMA BS transmitter and DTV receiver is 6.25 MHz for the worst case of urban environment. The analysis results may offer a reference and be helpful for considering interference between DTV and other communication systems.

A New CMOS IC Package Design Methodology Based on the Analysis of Switching Characteristics (CMOS IC 패키지의 스위치 특성 해석 및 최적설계)

  • 박영준;어영선
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1141-1144
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    • 1998
  • A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

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Robust control of linear systems under structured nonlinear time-varying perturbations I - Analysis

  • Bambang, Riyanto-T.;Shimemura, Etsujiro
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10b
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    • pp.81-87
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    • 1993
  • In this paper robust stability conditions are obtained for linear dynamical systems under structured nonlinear time-varying perturbations, using absolute stability theory and the concept of dissipative systems. The conditions are expressed in terms of solutions to linear matrix inequality(LMI). Based on this result, a synthesis methodology is developed for robust feedback controllers with worst-case H$_{2}$ perforrmance via convex optimization and LMI formulation.

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On a Two Dimensional Linear Programming Knapsack Problem with the Extended GUB Constrain (확장된 일반상한제약을 갖는 이차원 선형계획 배낭문제 연구)

  • Won, Joong-Yeon
    • Journal of Korean Institute of Industrial Engineers
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    • v.27 no.1
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    • pp.25-29
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    • 2001
  • We present a two dimensional linear programming knapsack problem with the extended GUB constraint. The presented problem is an extension of the cardinality constrained linear programming knapsack problem. We identify some new properties of the problem and derive a solution algorithm based on the parametric analysis for the knapsack right-hand-side. The solution algorithm has a worst case time complexity of order O($n^2logn$). A numerical example is given.

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Analysis of Worst Case Execution Time of Tasks with Cheekpointing in Real-Time Systems (실시간 시스템에서 검사점 작성을 하는 태스크의 최악 수행시간 분석)

  • 김상수;홍지만;조유근
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.04a
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    • pp.184-186
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    • 2004
  • 검사점 작성을 이용하는 실시간 태스크의 스케줄링 가능성을 알기 위한 선행 조건으로 최악 수행시간을 분석하고 이를 최소로 하는 효율적인 검사점 작성의 위치를 결정하는 방법을 제시한다. 여기서 사용하는 조건은 k 개의 연속적인 결함을 허용하고 태스크의 검사점 작성 비용이 고정적인 경우와 가변적인 경우를 가정한다. 이러한 각 조건에서 최악 수행 시간을 최소로 하는 검사점 작성 알고리즘을 제시한다.

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LPT Scheduling for Multipurpose Machines (여러 종류의 작업 처리가 가능한 기계 시스템에 대한 LPT 스케줄링)

  • Hwang, Hark-Chin
    • IE interfaces
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    • v.16 no.spc
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    • pp.132-137
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    • 2003
  • We consider scheduling jobs on multipurpose machines where jobs can be processed by a subset of the machines operated in parallel with the objective of minimizing makespan. We apply LPT(Longest Processing Time first) algorithm and prove that its posterior worst-case performance ratio is at most $log_24m/(1+{\lambda})$, where \lambda is the number of machines eligible for processing the job with the latest completion time. In general, LPT is shown to always find a schedule with makespan at most $log_24m/3$ times optimum.

Timing Analysis for Satellite Flight Software (인공위성 소프트웨어 타이밍 분석)

  • 이종인;최종욱;이재승;강수연
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10b
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    • pp.367-369
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    • 2003
  • 인공위성 탑재 소프트웨어는 정해진 시간 내에 필요한 작업을 수행하여야 하는 실시간 내장형 소프트웨어로 타이밍 분석이 중요하다. 기존의 인공위성소프트웨어 개발 시 적용되는 타이밍 분석기법은 개발자의 수작업에 의존하여 많은 시간과 노력이 요구되며 정확성에 문제가 있을 수 있는 단점이 있었다. 본 논문에서는 위성소프트에어의 타이밍 분석에 적용 가능한 최장 실행시간 (Worst Case Execution Time, WCET) 기법을 조사하고 보다 정확한 (tight) WCET를 구하기 위해 입력 데이터를 고려한 WCET 분석 방안을 제안한다.

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