• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.1-7
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• 2010

The device performances of accumulation-mode Pi-gate pMOSFETs with different fin widths have been characterized at high operating temperatures. The device fin height is 10nm and fin widths are 30nm, 40nm, and 50nm. The variation of the drain current, threshold voltage, subthreshold swing, effective mobility, and leakage current have been investigated as a function of operating temperatures. The drain current at high temperature is slightly larger than at room temperature. The variation of the threshold voltage as a function of the operating temperature is smaller than that of the inversion-mode MOSFETs. The effective mobility is decreased with the increase of operating temperature. It is observed that the effective mobility is enhanced as the fin width decreases.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.3
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• pp.175-181
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• 2015

In this paper, the neuromuscular electrical stimulation medical devices for non-implantable incontinence treatment other than vaginal insertion type was developed and commercialized. The structure of medical devices for electrical stimulation based on the anatomy of the pelvic floor muscle designed. Then, the optimum parameters that may be effective in pelvic floor muscle electrical stimulation was set. The circuit system based on the optimum parameters were designed and manufactured. The frequency of the pulse voltage for electrical stimulation is 75[Hz], the pulse width is 300[${\mu}s$], the development of medical devices was to have seven program functions to the various treatments. The circuit system of medical devices was composed of microcontroller, comparator and converter. The performance of the developed circuit system in KTC(Korea Testing Certification) were carried out medical equipment inspection test. Test results, test specifications were satisfied with the medical device, the performance was verified to be commercialized as a medical device. The development of medical devices were validated risk assessment and product performance through a software validation. Commercialization of medical equipment was acquired to enable the certification standards of the international standard IEC 60601-1.

• Transactions on Electrical and Electronic Materials
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• v.2 no.1
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• pp.32-38
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• 2001

A new small sized Lateral Trench electrode Insulated Gate Bipolar Transistor(LTEIGBT) was proposed to improve the characteristics of conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire electrode of LTEIGBT was replace with trench-type electrode. The LTEIGBT was designed so that the width of device was no more than 19 ㎛. The Latch-up current densities of LIGBT, LTIGBT and the proposed LTEIGBT were 120A/㎠, 540A/㎠, and 1230A/㎠, respectively. The enhanced latch-up capability of the LTEIGBT was obtained through holes in the current directly reaching the cathode via the p+ cathode layer underneath n+ cathode layer. The forward blocking voltage of the LTEIGBT is 130V. Conventional LIGBT and LTIGBT of the same size were no more than 60V and 100V, respectively. Because the the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and punch through breakdown of LTEIGBT is occurred, lately.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.5
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• pp.393-399
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• 2016

In this study, an experiment was conducted using a 3D scanner, commonly used in reverse engineering techniques, and the newly introduced CT measuring machine. The hole, width, and angle of specimens having various shapes were designated, the error rates in dimensional modelling generated during scanning with each device were compared, and the models were printed using a 3D printer. A secondary comparative analysis of the two printed specimens was conducted; the causes of dimension errors that occur during the printing process after scanning with each device and the differences associated with variation in shape were also analyzed. Based on the analysis results, the featured shape for each scanning application method and issues to consider in reverse engineering were presented, and the use of the CT measuring machine was recommended as a method to minimize error rates in dimensions and ensure efficient reverse engineering.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.57-65
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• 1995

The effects of device geometry and layout on high speed performance such as current gain outoff frequency(f$_{T}$) and maximum oscillation frequency(f$_{max}$) are of very improtant for the scaling-down of geterojunction bipolar transistors(HBT$_{s}$). In this paper AlGaAs/GaAs HBTs are fabricated by MBE epitaxial growth and conventional mesa process, and the experimental data of emitter-base geometru dependency of HBT performance are presented in order to provide the quantitative information for optimum device structure design. It is shown that f$_{T}$ and f$_{max}$ are inversely proportional to the emiter stripe width, while the low emitter perimeter/area ratio is better to f$_{T}$ and worse ot f$_{max}$. It is also demonstrated the f$_{T}$ and f$_{max}$ are highly improved by the emitter-base spacing reduction resulting in less parsitic effects. As the result f$_{T}$ of 42GHz and f$_{max}$ of 23GHz are obtained for fabricated HBT with emitter area of 3${\times}20^{\mu}m^{2}$ and E-B spacing of 0.2$\mu$m.m.m.

• Physical Therapy Korea
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• v.18 no.3
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• pp.16-25
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• 2011

This study aimed to evaluate factors related to the ability of ambulatory patients with cerebral palsy (CP) to walk over vertical and horizontal obstacles. Twenty patients with spastic CP who were able to walk independently for at least 10 m with or without walking devices were recruited for the study. Participants were required to walk over small obstacles (1, 4, and 8 cm in height or width; total of 6 conditions). A 'fail' was recorded when either the lower limbs or the walking device contacted the obstacle. Linear regression analyses were used to determine the effects of age, sex, walking devices, eyeglasses, subtype (hemiplegia or diplegia), ankle foot orthoses, functional level, and score of body mass index on the ability of obstacle crossing. Fifteen participants (75%) failed to adequately clear the foot or walking device over obstacles in at least 1 condition. The chance of failure in crossing vertical obstacle was affected by the use of ankle foot orthoses, eyeglasses, gender, and CP subtype (p<.05). The failure rate crossing horizontal obstacle was affected by CP subtype. These findings suggest that rehabilitation procedures should (1) consider the clinical characteristics of patients in order to prepare them to be more independent while performing daily activities, and (2) incorporate environmental conditions that patients encounter at home and in the community.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.128.2-128.2
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• 2014

Long-wave infrared detectors using the type-II InAs/GaSb strained superlattice (T2SL) material system with the nBn structure were designed and fabricated. The band gap energy of the T2SL material was calculated as a function of the thickness of the InAs and GaSb layers by the Kronig-Penney model. Growth of the barrier material (Al0.2Ga0.8Sb) incorporated Te doping to reduce the dark current. The full width at half maximum (FWHM) of the 1st satellite superlattice peak from the X-ray diffraction was around 45 arc sec. The cutoff wavelength of the fabricated device was ${\sim}10.2{\mu}m$ (0.12eV) at 80 K while under an applied bias of -1.4V. The measured activation energy of the device was ~0.128 eV. The dark current density was shown to be $1.2{\times}10^{-5}A/cm^2$ at 80 K and with a bias -1.4 V. The responsivity was 1.9 A/W at $7.5{\mu}m$ at 80K and with a bias of -1.9V.