• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.161-165
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• 2004

In this paper, an 8bit wave pipelined adder using the static CMOS plus Edge-Sensing Completion Detection Logic is presented. The clockless wave-pipelining algorithm was implemented in the circuit design. The Edge-Sensing Completion Detection (ESCD) in the algorithm is consisted of edge-sensing circuits and latches. Using the algorithm, skewed data at the output of 8bit adder could be aligned. Simulation results show that the adder operates at 1GHz in $0.35{\mu}m$ CMOS technology with 3.3V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.74-82
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• 1992

This paper deals with the scheduling problems, which are the most important subtask in High-level Synthesis. ILP(integer linear programming) formulations are used as a scheduling problem approach.For practical application to digital system design, we have concentrated our attentions on pipelined datapath scheduling. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule. Finally, we can obtain better and near-optimal scheduling results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.53-67
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• 1994

This paper describes the design of a high-level synthesis system. SODAS-VP. which automatically generates hardwares executing operation sequences in pipelined fashion.Target architecture and clocking schemes to drive pipelined datapath are determined, and the handling of pipeline hazards which degrade the performance of pipeline is considered. Partitioning of an operation into load, operation, and store stages, each of which is executed in partitiones control step, is performend. Pipelinecl hardware is generated by handling pipeline hazards with internal forwarding or delay insertion techniques in partitioning process and resolving resource conflicts among the partitioned control steps with similarity measure as a priority function in module allocation process. Experimental results show that SODAS-VP generates hardwares that execute faster than those generated by HAL and ALPS systems. SODAS-VP brings improvement in execution speed by 17.1% and 7.4% comparing with HAL and ALPS systems for a MCNC benchmark program, 5th order elliptical wave filter,respectively.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2973-2979
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• 1998

As this paper is a scheduling algorithm for the synthesis of a pipelined datapath under resource constraints in high level synthesis, the proposed heuristic algorithm uses a priority function based on the collision count of resourecs. In order to schedule the pipelined datapath under resource constraints, we define the collision count and the priority function based on the collision count, a number of resource, and the mobility of operations to resolve a resource collision. The proposed algorithm supports chaining, multicycling, and structural pipelining to design the realistic hardware. The evaluation of the Performance is compared with other systems using the results of the synthesis for a 16point FIR filter and a 5th order elliptic wave filter, where in most cases, the optimal solution is obtained.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.7
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• pp.37-45
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• 1998

A 32-b self-timed parallel carry look-ahead adder (PCLA) designed for 0.5.mum. single threshold low power CMOS technology is demonstrated to operate with 2.7nsec delay at 8mW under 1V power supply. Compared to static PCLA and DPL adder, the self-timed PCLA designed with NORA logic provides the best performance at the power consumption comparable to other adder structures. The wave pipelined clock control play a crucial role in achieving the low power, high performance of this adder by eliminating the unnecessary power consumption due to the short-circuit current during the precharge phase. Th enoise margin has been improved by adopting the physical design of staic CMOS logic structure with controlled transistor sizes.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.308-310
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• 2022

With the rise of the Al wave, task-oriented dialogue systems have become one of the popular research directions in academia and industry. Currently, task-oriented dialogue systems mainly adopt pipelined form, which mainly includes natural language understanding, dialogue state decision making, dialogue state tracking and natural language generation. However, pipelining is prone to error propagation, so many task-oriented dialogue systems in the market are only for single-round dialogues. Usually single- domain dialogues have relatively accurate semantic understanding, while they tend to perform poorly on multi-domain, multi-round dialogue datasets. To solve these issues, we developed a paddle-based multi-domain task-oriented Chinese dialogue system. It is based on NEZHA-base pre-training model and CrossWOZ dataset, and uses intention recognition module, dichotomous slot recognition module and NER recognition module to do DST and generate replies based on rules. Experiments show that the dialogue system not only makes good use of the context, but also effectively addresses long-term dependencies. In our approach, the DST of dialogue tracking state is improved, and our DST can identify multiple slotted key-value pairs involved in the discourse, which eliminates the need for manual tagging and thus greatly saves manpower.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.