• Title/Summary/Keyword: wafer warpage

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Analysis of the shrinkage and warpage of Wafer lens during UV curing (Lens 성형시 UV경화 반응에 따른 수축 및 변형 대한 해석적 접근)

  • Park, Sihwan;Moon, Jong-Sin
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.11
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    • pp.6464-6471
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    • 2014
  • The UV curing method is a popular process for lens molding on a unit wafer. This process, however, has several drawbacks including wafer adhesion during the ejection process after curing, errors in lens shape and wafer warpage due to material shrinkage during the curing process, and lens centering errors on both sides of a wafer. Among these, the lens shape error and warpage are influenced directly by the UV curing process due to factors including the UV radiation uniformity, the degree of cure according to UV intensity, and the shrinkage characteristics of the material. Therefore, a theory is needed not only to understand the change in the material characteristics, such as the shrinkage rate due to the curing reaction, but also to establish a model. In addition, an analysis system is needed to realize the model. This study proposes a new analysis method for the wafer lens molding process by Comsol modeling. This method was verified by comparing the results with those of the actual process.

Effect of Material Property Uncertainty on Warpage during Fan Out Wafer-Level Packaging Process (팬아웃 웨이퍼 레벨 패키지 공정 중 재료 물성의 불확실성이 휨 현상에 미치는 영향)

  • Kim, Geumtaek;Kang, Gihoon;Kwon, Daeil
    • Journal of the Microelectronics and Packaging Society
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    • v.26 no.1
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    • pp.29-33
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    • 2019
  • With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

Wafer Level Package Design Optimization Using FEM (공정시간 및 온도에 따른 웨이퍼레벨 패키지 접합 최적설계에 관한 연구)

  • Ko, Hyun-Jun;Lim, Seung-Yong;Kim, Hee-Tea;Kim, Jong-Hyeong;Kim, Ok-Rae
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.23 no.3
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    • pp.230-236
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    • 2014
  • Wafer level package technology is added to the surface of wafer circuit packages to create a semiconductor technology that can minimize the size of the package. However, in conventional packaging, warpage and fracture are major concerns for semiconductor manufacturing. We optimized the wafer dam design using a finite element method according to the dam height and heat distribution thermal properties. The dam design influences the uniform deposition of the image sensor and prevents the filling material from overflowing. In this study, finite element analysis was employed to determine the key factors that may affect the reliability performance of the dam package. Three-dimensional finite element models were constructed using the simulation software ANSYS to perform the dam thermo-mechanical simulation and analysis.

Effects of Package Induced Stress on MEMS Device and Its Improvements (패키징으로 인한 응력이 MEMS 소자에 미치는 영향 분석 및 개선)

  • Choa Sung-Hoon;Cho Yong Chul;Lee Moon Chul
    • Journal of the Korean Society for Precision Engineering
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    • v.22 no.11 s.176
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    • pp.165-172
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    • 2005
  • In MEMS (Micro-Electro-Mechanical System), packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. In the decoupled vibratory MEMS gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. This effect results in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) process technology. It uses a silicon wafer and two glass wafers to minimize the wafer warpage. Thus the warpage of the wafer is greatly reduced and the frequency difference is more uniformly distributed. In addition. in order to increase robustness of the structure against deformation caused by EMC molding, a 'crab-leg' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

Development of Cu CMP process for Cu-to-Cu wafer stacking (Cu-to-Cu 웨이퍼 적층을 위한 Cu CMP 특성 분석)

  • Song, Inhyeop;Lee, Minjae;Kim, Sungdong;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.81-85
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    • 2013
  • Wafer stacking technology becomes more important for the next generation IC technology. It requires new process development such as TSV, wafer bonding, and wafer thinning and also needs to resolve wafer warpage, power delivery, and thermo-mechanical reliability for high volume manufacturing. In this study, Cu CMP which is the key process for wafer bonding has been studied using Cu CMP and oxide CMP processes. Wafer samples were fabricated on 8" Si wafer using a damascene process. Cu dishing after Cu CMP and oxide CMP was $180{\AA}$ in average and the total height from wafer surface to bump surface was approximately $2000{\AA}$.

Position Control of Wafer Lift Pin for the Reduction of Wafer Slip in Semiconductor Process Chamber

  • Koo, Yoon Sung;Song, Wan Soo;Park, Byeong Gyu;Ahn, Min Gyu;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.4
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    • pp.18-21
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    • 2020
  • Undetected wafer slip during the lift pin-down motion in semiconductor equipment may affect the center to edge variation, wafer warpage, and pattern misalignment in plasma equipment. Direct measuring of the amount of wafer slip inside the plasma process chamber is not feasible because of the hardware space limitation inside the plasma chamber. In this paper, we demonstrated a practice for the wafer lift pin-up and down motions with respect to the gear ratio, operating voltage, and pulse width modulation to maintain accurate wafer position using remote control linear servo motor with an experimentally designed chamber mockup. We noticed that the pin moving velocity and gear ratio are the most influencing parameters to be control, and the step-wised position control algorithm showed the most suitable for the reduction of wafer slip.

Development of Automatic Bonding System for GaAs Wafer (GaAs Wafer 접합용 본딩시스템 개발)

  • Song J.Y.;Kang J.H.;Lee C.W.;Ha T.H.;Jee W.H.;Kim W.K.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.427-431
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    • 2005
  • In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

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