• Journal of the Semiconductor & Display Technology
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• v.9 no.1
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• pp.23-28
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• 2010

In this paper, wafer drop from wafer guide mechanism, which is one of the serious problems in water transfer robot, is analyzed, and new wafer guide mechanisms are proposed to minimize this drop. Three types of new wafer guide mechanisms are proposed: roller type, gear type and L-shape rocker type. We choose one of the proposed mechanism, which is roller type, and verified this mechanism through real transfer experiment. Wafer picking up test is conducted with initial aligning error for simulating the wafer drop. Number of drop is compared between conventional mechanism and proposed mechanism. As a result, we can find the proposed mechanism can reduce the number of wafer drop dramatically.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.65-69
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• 2010

In this study, we investigated the effects of UBM(Under Bump Metallization) and solder composition on the drop impact reliability of wafer level packaging. Fan-in type WLP chips were prepared with different solder ball composition (Sn3.0Ag0.5Cu, and Sn1.0Ag0.5Cu) and UBM (Cu 10 ${\mu}m$, Cu 5 ${\mu}m$\Ni 3 ${\mu}m$). Drop test was performed up to 200 cycles with 1500G acceleration according to JESD22-B111. Cu\Ni UBM showed better drop performance than Cu UBM, which could be attributed to suppression of IMC formation by Ni diffusion barrier. SAC105 was slightly better than SAC305 in terms of MTTF. Drop failure occurred at board side for Cu UBM and chip side for Cu\Ni UBM, independent of solder composition. Corner and center chip position on the board were found to have the shortest drop lifetime due to stress waves generated from impact.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1892-1897
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• 2003

A new thermal inkjet printer head on SOI wafer with virtual valve was proposed. It was composed of two rectangular heaters with same size. So we could call it T-jet(Twin jet). T-jet has a lot of merits. It has the advantage of being fabricated with one wafer and is easy to change the size of chamber, nozzle, restrictor and so on. However, above all, It is the best point that T-jet has a virtual valve. And it was manufactured on SOI wafer. The chamber was formed in its upper silicon whose thickness was 40um. The chamber's bottom layer was silicon dioxide of SOI wafer and two heaters were located underneath the chamber's ceiling. And the restirctor was made beside the chamber. Nozzle was molded by process of Ni plating. Ni was 30um thick. Nozzle ejection test was performed by printer head having 56 nozzles in 2 columns with 600NPI(nozzle per inch) and black ink. It measured a drop velocity of 12m/s, a drop volume of 30pl, and a maximum firing frequency of 12KHz for single nozzle ejection. Throwing out the ink drop in whole nozzles at the same time, it was observed that the uniformity of the drop velocity and volume was less than 4%.

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• Particle and aerosol research
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• v.18 no.4
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• pp.129-136
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• 2022

The line width of circuits in semiconductor devices continues to decrease down to a few nanometers. Since nanoparticles attached to the patterned wafer surface may cause malfunction of the devices, it is crucial to remove the contaminant nanoparticles. Physical cleaning that utilizes momentum of liquid for detaching solid nanoparticles has recently been tested in place of the conventional chemical method. Dropwise impaction has been employed to increase the removal efficiency with expectation of more efficient momentum exchange. To date, most of relevant studies have been focused on drop spreading behavior on a horizontal surface in terms of maximum spreading diameters and average spreading velocity of drop. More important is the local liquid velocity at the position of nanoparticle, very near the surface, rather than the vertical average value. In addition, there are very scarce existing studies dealing with microdroplet impaction that may be desirable for minimizing pattern demage of the wafer. In this study, we investigated the local velocity distribution in spreading liquid film under various impaction conditions through the CFD simulation. Combining the numerical results with the particle removal model, we estimated an effective cleaning diameter (ECD), which is a measure of the particle removal capacity of a single drop, and presented the predicted ECD data as a function of droplet's velocity and diameter particularly when the droplets are microns in diameter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Journal of Mechanical Science and Technology
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• v.19 no.6
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• pp.1338-1346
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• 2005

Effects of thermal contact resistance between heater and susceptor, susceptor and graphite board in a MOCVD reactor on temperature distribution and film growth rate were analyzed. One-dimensional thermal resistance model considering thermal contact resistance and heat transfer area was made up at first to find the temperature drop at the surface of graphite board. This one-dimensional model predicted the temperature drop of 18K at the board surface. Temperature distribution of a reactor wall from the three-dimensional computational fluid dynamics analysis including the gap at the wafer position showed the temperature drop of 20K. Film growth rates of InP and GaAs were predicted using computational fluid dynamics technique with chemical reaction model. Temperature distribution from the three-dimensional heat transfer calculation was used as a thermal boundary condition to the film growth rate simulations. Temperature drop due to the thermal contact resistance affected to the GaAs film growth a little but not to the InP film growth.

• Tribology and Lubricants
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• v.32 no.2
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• pp.44-49
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• 2016

Diamond mechanical polishing (DMP) is a crucial process in a sapphire wafering process to improve flatness and achieve the target thickness by using free abrasives. In a DMP process, material removal rate (MRR) is a key factor to reduce process time and cost. Controlling mechanical parameters, such as velocity and pressure, can increase the MRR in a DMP process. However, there are limitations of using high velocities and pressures for achieving a high MRR owing to their side effects. In this paper, we present the lapping characteristics and improvement of MRR by using a fixed abrasive plate through an experimental study. The change in MRR as a function of velocity and pressure follows Preston's equation. The surface roughness of a wafer decreases as the plate velocity and pressure increases. We observe a sharp decrease in MRR over the lapping time at a high velocity and pressure in the velocity and pressure test. An analysis of surface roughness (Rq and Rpk) indicates that wear of abrasives decreases the MRR sharply. In order to investigate the effect of abrasive wear on the MRR, we utilize a cutting fluid and a rough wafer. The cutting fluid delays the wear of abrasives resulting in improvement of MRR drop. The rough wafer maintains the MRR at a stable rate by self-dressing.

• Bulletin of the Korean Chemical Society
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• v.26 no.6
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• pp.966-970
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• 2005

To measure the thickness of liquid films from 10 to 60 ${\mu}m$, we used photochromic dye activation. And we used silicone oil with 10 centi-Stokes and commercial photochromic dyes. To make films with exact and known thicknesses, we used two glass wafers. A film formed between two wafers after placing a drop of liquid of known volume on one wafer and covering the other. The film thickness could be estimated from the diameter of wafer and the dropped liquid volume. To quantitatively evaluate the result, captured the images using digital camera then analyzed the images using the image tool. The gray scale intensity using the captured images of activated dye with these thicknesses showed the repeatability below ${\pm}$ 1.0% when measured with a silicone oil solution containing 0.1% SO and SO-ANTH dyes. And we showed that photochromic dye activation method could be used to measure our liquid film thickness ranges.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.225-228
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• 2000

In this paper, we demonstrated an analytical description method of forward voltage drop and reverse voltage of $P^{+}N$ junction diode with <111> oriented antimony doped silicon wafer 60keV boron implantation computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 1min at $1000^{\circ}C$ inert gas condition.