• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.239-246
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• 2003

The Verilog parser libary for IEEE Verilog 1364-2001 Standard is developed in the paper. The lexer and scanner are developed and tested to handle "Yerilog-2001" which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is presented. By using the XML intermediate, it allows the portable and scalable development of various kinds of verilog applications that are mainly focused on semantic manipulation.ipulation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.212-215
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• 2000

This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.309-314
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• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1177-1180
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• 2003

Recently, SystemC is one among the language observed. In Industry, there are many the languages that use Verilog. But, unskillful SystemC users must learn SystemC for conversion that from Verilog to SystemC and need time and effort for this. By these reason, feel necessity of easy and efficient conversion. This paper argues efficient methodology to change Verilog to SystemC. Abstract concepts of Verilog are proposed fittingly each one by one in SystemC.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.97-100
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• 2002

A procedural interface libary for IEEE Verilog 1364-2001 is developed. The lexer and scanner are developed to handle “Verilog-2001” which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is Presented in the paper. By using the XML intermediate, it allows the portable and scalable development of various kinds of applications. The XML DTD(Document Type Definition) of Verilog is defined and the corresponding XML intermediate format is developed. The paper describes example application of code rule checker which is built using the language interface library.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.4
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• pp.274-279
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• 2009

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, verification environments based-on SystemVerilog and SystemC, one is native-code co-verification environment which makes prompt functional verification possible and another is SystemVerilog layered testbench which makes clock-level verification possible, are implemented. In native-code co-verification, HW and SW parts of SoC are respectively designed with SystemVerilog and SystemC after HW/SW partitioning using SystemC, then the functional interaction between HW and SW parts is carried out as one simulation process. SystemVerilog layered testbench is a verification environment including corner case test of DUT through the randomly generated test-vector. We adopt SystemC to design a component of verification environment which has multiple inheritance, and we combine SystemC design unit with the SystemVerilog layered testbench using SystemVerilog DPI and ModelSim macro. As multiple inheritance is useful for creating class types that combine the properties of two or more class types, the design of verification environment adopting SystemC in this paper can increase the code reusability.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.599-602
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• 2014

본 논문은 FBDtoVerilog 변환기의 correctness 검증을 지원하는 시나리오 생성기에 대해 소개한다. 현재 원자력 발전소의 제어기는 PLC 를 이용하여 개발되고 있지만, 최근 FPGA 를 이용한 제어기 개발의 필요성이 증가하고 있다. 우리는 이를 지원하기 위해 PLC 개발에 사용되는 언어인 FBD를 FPGA 에 사용되는 언어인 Verilog 로 자동 변환하는 변환기 FBDtoVerilog 를 개발 하였다. 하지만 원자력 발전소와 같은 안전 필수 시스템은 철저하고 엄격한 검증 과정이 필수 이기 때문에, 우리는 FBDtoVerilog 를 검증할 수 있는 Co-Simulation 환경을 구축하여 검증할 계획을 가지고 있다. Co-Simulation 환경을 위한 첫 번째 단계로 자동화된 시나리오 생성기를 개발 하였다. 개발된 시나리오 생성기는 도메인 특징을 반영한 시나리오를 생성할 수 있고, 무한한 개수의 시나리오를 자동으로 생성할 수 있는 장점을 가지고 있다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.30-38
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• 2003

UDP library of Verilog HDL has been used for simulation of digital systems. But it takes a lot of time and efforts to generate a gate-level library equivalent to the UDP library manually due to the characteristic of UDP that does not support synthesis. It is indispensable to generate equivalent gate-level model in testing the digital systems because fault coverage can be reduced without the equivalent gate-level models. So, it is needed to automate the process of generating the equivalent gate-level models. An algorithm to solve this problem has been proposed, but it is unnecessarily complex and time-consuming. This paper suggests a new improved algorithm to implement the conversion to gate-level models, which exploits the characteristic of UDP Experimental results are demonstrated to show the effectiveness of the new algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.656-658
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• 2013

Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to the design of an elliptic curve crypto-engine server farm. I successfully implemented the whole system including the test bench in one integrated environment, otherwise in the traditional way it would have cost Verilog simulation and C/SystemC verification which means much more time and effort.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.