• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.6
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• pp.241-251
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• 2002

The effect of sensor faults in direct torque control(DTC) based induction motor drives is analyzed and a new Instrument fault detection isolation scheme(IFDIS) is proposed. The proposed IFDIS, which operated in real-time, detects and isolates the incipient fault(s) of speed sensor and current sensors that provide the feedback information. The scheme consists of an adaptive gain scheduling observer as a residual generator and a special sequential test logic unit. The observer provides not only the estimate of stator flux, a key variable in DTC system, but also the estimates of stator current and rotor speed that are useful for fault detection. With the test logic, the IFDIS has the functionality of fault isolation that only multiple estimator based IFDIS schemes can have. Simulation results for various type of sensor faults show the detection and isolation performance of the IFDIS and the applicability of this scheme to fault tolerant control system design.

• Proceedings of the IEEK Conference
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• summer
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• pp.221-224
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• 2004

This paper proposed an ultra low-power CMOS exponential voltage-mode circuit using the Pseudo-exponential function for realizing the exponential characteristics. The proposed circuit provides high dB-linear output voltage range at low-voltage applications. In a $0.25\;\mu m$ CMOS process, the simulations show more than 35 dB output voltage range and 26 dB with the linearity error less than $\pm0.5\;dB.$ The average current consumption is less than 80 uA. The proposed circuit can be used for the design of an extremely low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1063-1066
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• 2000

ln this paper, a new active phase shifter is proposed using a vector sum method, and it is shown that the proposed phase shifter is more efficient than the others in size, power, number of circuits, and gain. Also a unique digital phase control method of the circuit is suggested. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line 3dB quadrature hybrid coupler and variable gain amplifiers (VGAs) using dual gate FETs (DGFETs). Furthermore, it is also shown that the proposed scheme is more efficient and works properly with the digital phase control method.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• KIEE International Transactions on Power Engineering
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• v.3A no.1
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• pp.17-26
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• 2003

In this paper, the comparative steady-state operating performance analysis algorithms of the stand-alone single-phase self-excited induction generator (SEIG) is presented on the basis of the two nodal admittance approaches using the per-unit frequency in addition to a new state variable de-fined by the per-unit slip frequency. The main significant features of the proposed operating circuit analysis with the per-unit slip frequency as a state variable are that the fast effective solution could be achieved with the simple mathematical computation effort. The operating performance results in the simulation of the single-phase SEIG evaluated by using the per-unit slip frequency state variable are compared with those obtained by using the per-unit frequency state variable. The comparative operating performance results provide the close agreements between two steady-state analysis performance algorithms based on the electro-mechanical equivalent circuit of the single-phase SEIG. In addition to these, the single-phase static VAR compensator; SVC composed of the thyristor controlled reactor; TCR in parallel with the fixed excitation capacitor; FC and the thyristor switched capacitor; TSC is ap-plied to regulate the generated terminal voltage of the single-phase SEIG loaded by a variable inductive passive load. The fixed gain PI controller is employed to adjust the equivalent variable excitation capacitor capacitance of the single-phase SVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.4
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• pp.55-61
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• 1995

Variable structure control (VSC) can be used for the control of power plants required stability and robustness such as elevator control. It has no overshoot and is insensitive to parameter variations and disturbances in the sliding mode where the system structure is changed with the sliding surface in the center. But in the real system, VSC has a high frequency chattering which has a bad influence upon the control system proformances. In this paper, to alleviate the high frequency chattering, a binary controller (BC) with inertial type external loop is implemented by DSP and applied to position control of brushless DC motor. Binary controller has external loop to generate the continuous control input with the flexible variation of primary loop gain. Thus it has the property of chattering alleviation in addition to advantages of the conventional variable structure control.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.21 no.9
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• pp.1462-1469
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• 1997

This study presents a genetic algorithm-based method for optimizing control parameters in fluid power systems. Genetic algorithms are general-purpose optimization methods based on natural evolution and genetics. A genetic algorithm seeks control parameters maximizing a measure that evaluates system performance. Five control gains of the PID-PD cascade controller fr an electrohydraulic speed control system with a variable displacement hydraulic motor are optimized using a genetic algorithm in the experiment. Optimized gains are confirmed by inspecting the fitness distribution which represents system performance in gain spaces. It is shown that optimization of the five gains by manual tuning should be a task of great difficulty and that a genetic algorithm is an efficient scheme giving economy of time and in labor in optimizing control parameters of fluid power systems.

• Journal of Satellite, Information and Communications
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• v.3 no.1
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• pp.1-7
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• 2008

This Paper studied the design and measured results of a flight model for Ku-Band Linearized Channel Amplifier (LCAMP) for communication satellite onboard system. All MMICs, i.e. Variable Gain Amplifier (VGA), Variable Voltage Attenuator (VVA) with analog/digital attenuator, Branch line Hybrid Coupler and Detector for Pre-distorter are fabricated using Thin-Film Hybrid process. The performance of the fabricated module is verified through Radio Frequency circuit simulations and electrical function test in space environment for flight model at 12.25 to 12.75 GHz.