• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.260-264
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• 2010

In this paper, Ni silicide is formed on boron cluster ($B_{18}H_{22}$) implanted source/drains for shallow junctions of nano-scale CMOSFETs and its thermal stability is improved, using vacuum annealing. Although Ni silicide on $B_{18}H_{22}$ implanted Si substrate exhibited greater sheet resistance than on the $BF_2$ implanted one, its thermal stability was greatly improved using vacuum annealing. Moreover, the boron depth profile, using vacuum post-silicidation annealing, showed a shallower junction than that using $N_2$ annealing.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.47-53
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• 2007

Ultra thin Si p-n junctions shallower than $300{\AA}$ were fabricated and biased to the avalanche regime. The ultra thin junctions were fabricated to be parallel to the surface and exposed to the surface without $SiO_2$ layer. Those junctions emitted white light and electrons when junctions were biased in the avalanche breakdown regime. Therefore, we could observe the avalanche breakdown region visually. We could also observe the influence of electric field to the current flow visually by observing the white light which correspond to the avalanche breakdown region. Arrayed diodes emit light and electrons uniformly at the diode area. But, the reverse leakage current were larger than those of ordinary diodes, and the breakdown voltage were less than 10V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2002.06a
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• pp.57-57
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• 2002

• Proceedings of the Korean Vacuum Society Conference
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• 2001.07a
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• pp.53-53
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• 2001

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.603-606
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• 2005

In this paper, the formation and thermal stability of Ni-silicide using Ni-Pd alloys is studied for ultra shallow S/D junction of nano-scale CMOSFETs. There are no different effects when Ni-Pd is used in single structure and TiN capping structure. But, in case of Cobalt interlayer structure, it was found that Pure Ni had lower sheet resistance than Ni-Pd, because of a thick silicide. Also, Ni-Pd has merits that surface of silicide and interface between silicide and silicon have a good morphology characteristics. As a result, Ni-Pd is an optimal candidate for shallow S/D junction when cobalt is used for thermal stability.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.89-98
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• 1992

IIM(Implantation Into Metal) process usning Co silicides has been investigated to obtain ultra-shallow junctions less than 0.1$\mu$m. Rapid Thermal Annealing using halogen lamps was employed to form CoSi$_2$ and junctions simultaneously.. Resistivities of CoSi$_2$ were 13-17$\mu$ $\Omega$-cm. CoSi$_2$/p$^{+}$/Si and CoSi$_2$/n$^{+}$/Si junction were formed by diffusion of B and As, respectively, from Co film. It was found out that B and As were severely lost by the evaporation during high temperature annealing Therefore SiO$_2$ capping layers were introduced to prevent the evaporation of the implanted dopants from the films. Investigation of the behavior of dopants with respect to annealing time revealed that increasing the annealing time enhanced the diffusion of dopants into Si from CoSi$_2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.