• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.841-847
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• 2009

In this paper we propose a high-performance Hybrid ARQ scheme employing Chase combining based on LDPC (Low-Density Parity-Check) codes. The proposed scheme uses symbol mapping diversity and turbo demodulation to improve decoding performance. We analyze the performance of the proposed scheme by EXIT (EXtrinsic Information Transfer) chart and compare its performance with several symbol mappings.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.11-21
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• 2008

In conventional video coding, the complexity of encoder is much higher than that of decoder. However, as more needs arises for extremely simple encoder in environments having constrained energy such as sensor network, much investigation has been carried out for eliminating motion prediction/compensation claiming most complexity and energy in encoder. The Wyner-Ziv coding, one of the representative schemes for the problem, reconstructs video at decoder by correcting noise on side information using channel coding technique such as turbo code. Since the encoder generates only parity bits without performing any type of processes extracting correlation information between frames, it has an extremely simple structure. However, turbo decoding errors occur in noisy side information. When there are high-motion or occlusion between frames, more turbo decoding errors appear in reconstructed frame and look like Salt & Pepper noise. This severely deteriorates subjective video quality even though such noise rarely occurs. In this paper, we propose a computationally extremely light encoder based on symbol-level Wyner-Ziv coding technique and a new corresponding decoder which, based on a decision whether a pixel has error or not, applies median filter selectively in order to minimize loss of texture detail from filtering. The proposed method claims extremely low encoder complexity and shows improvements both in subjective quality and PSNR. Our experiments have verified average PSNR gain of up to 0.8dB.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.73-79
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• 2006

Due to the powerful correcting performance, turbo codes have been adopted in many communication standards such as W-CDMA(Wideband Code Division Multiple Access), CDMA2000, etc., and implemented by hardware in many kind of fields. Although several hardware structures and improved algorithm have been proposed, these problems such as hardware area, operating speed and power consumption are still a major issue to be solved in practical implementations. In this paper, we designed the turbo-code decoder using MAX -SCALE operation derived from the posterior probability optimization. The proposed circuit has been measured their performance on Matlab and MaxPlusII and implemented on the FPGA As a result, when implementing the proposed algorithm on the FPGA, this circuit only occupies 616 logic elements. And comparing the performance with the MAP(Maxirnum a Posteriori) decoding algorithm, the operating speed was increased by about 40%(56.48MHz) and BER(Bit Error Rate) was increased by 6.12.

• Journal of Internet Computing and Services
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• v.8 no.4
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• pp.61-70
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• 2007

In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST(Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP Decoder in decoding Algorithm of V-BLAST: ordering and slicing. And comparing the proposed system with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance and SNR has been improved. In addition, we show that the proposed system using STD(Selection Transmit Diversity) scheme results in on improved result, By using simulation and comparing to conventional Turbo Coded V-BLAST technique with the Adaptive Modulation systems, the optimal Turbo Coded V-BLAST technique with the Adaptive Modulation systems has SNR gain over all SNR range and better throughput gain that is about 350Kbps in 11dB SNR range. Also, comparing with the conventional Turbo Coded V-BLAST technique using 2 transmit and 2 receive antennas, the proposed system with STD scheme show that the improvement of maximum throughput is about 1.77Mbps in the same SNR range and the SNR gain is about 5.88dB to satisfy 4Mbps throughput performance.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.257-265
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• 2000

Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics in each decoding step, and uses the information to the next decoding step. Viterbi decoder, which is for a convolutional code, runs continuous mode, while Turbo Code decoder runs by block unit. There are algorithms used in a decoder : which are MAP(maximum a posteriori) algorithm requiring very complicated calculation and SOVA(soft output Viterbi algorithm) using Viterbi algorithm suggested by Hagenauer, and it is known that the decoding performance of MAP is better. The result of this make experimentation shows that the performance of SOVA, which has half complex algorithm compare to MAP, is almost same as the performance of MAP when the SOVA decoding performance is supplemented with Robust equalization techniques.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.107-113
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• 2013

Mobile mobility and data reliability should be guaranteed as well as amounts of data services are essential in the era of smart media. In order to improve the reliability of high-speed data, strong channel coding and modulation techniques are required. In this paper, the structure of Turbo TCM decoder, applying high-order modulation techniques and the DPSAM method which improves performances in time-selective fading channels in the case of burst errors are suggested through the optimal decoding method and iteration decoding so as to improve bandwidth efficiency in Turbo Codes with excellent encoding gain. The proposed method in comparison with the existing method is that 3dB is superior in case that BER is $10^{-2}$ and the number of iterations is 3. In addition, the function is improved at approximately 6dB in case that BER is $10^{-3}$ and the number of iterations is 7. The proposed method requires additional bandwidth; however, the bandwidth loss can be overcome through Turbo TCM technology on the additional bit rate from the bandwidth loss.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.423-426
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• 2005

In this paper, we propose a receiver that combines a channel detector with a channel decoder to retrieve information from ISI and AWGN in an iteratively manner. The receiver, evolving from a system of a PRML detector and a RS decoder, consists of a SOVA detector followed by a LDPC decoder and has them exchange information iteratively. Rather than handling extrinsic reliabilities explicitly as in Turbo equalization, we take hard-decision values from the LDPC decoder and mix them with the channel output in a certain ratio as input for SOVA. The scheme, simply modified to the one-way structure of a SOVA and a LDPC decoder, shows improved performance with iteration numbers as well as the combining ratio of the channel output and the feedback output. We additionally analyze the receiver with a simple theoretical model and present some valuable properties.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.426-432
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• 2007

The MAP algorithm is designed and implemented through the sliding window method for turbo decoding. First, the implementation issues, which are the length of the sliding window and the normalization method of state metrics are reviewed, and their optimal values are obtained by the simulation. All component schemes of the decoder including the branch metric evaluator are also presented. The proposed MAP architecture can be easily redesigned according to the size of sliding window, that is, sub-frame length because of its simplicity on buffer control.