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Architecture Design of Turbo Codec using on-the-fly interleaving

On-the-fly 인터리빙 방식의 터보코덱의 아키텍쳐 설계

  • Published : 2003.04.01

Abstract

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

본 논문에서는 IMT-2000용 터보코덱의 개선된 아키텍쳐를 제안하였다. 이는 on-the-fly 인터리빙 쉬프트 레지스터를 이용하여 외부 RAM을 사용하지 않는 인터리버에 의한 부호기와 필요한 메모리의 양을 줄이기 위한 복호기로 구성되었다. 제안된 구조는 C/VHDL 언어를 이용하여 시뮬레이션을 수행하여 반복횟수, 인터리버 블록크기, 부호율에 따른 비트오류율 성능이 이전 데이터와 비교적 일치함을 확인하였다.

Keywords

References

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