• 대한전자공학회논문지
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• 제26권6호
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• pp.124-130
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• 1989

ITIC를 중심으로 고밀도 DRAM을 위한 획기적인 밀도 향상을 기할 수 있는 공정과정과 회로디자인의 기술 혁신에 대하여 지다이너 입장에서 논의하였다. 여기서 개발한 TETC라 부르는 DRAM은 trench 기술과 SEG기술을 이용하였는데 $n^+-polysilycon$인 storage 전극과 $n^+-source$ 전극이 self-con-tact되고 soft error 를 극복할 만큼 충분히 큰 정전용량을 갖으므로 절연 영역을 따라서 만든 수직의 캐패시터를 이용함으로써 셀 크기를 기존의 BSE cell구조에 비하여 약 30% 감소되었다.

• 반도체디스플레이기술학회지
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• 제8권2호
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• pp.59-62
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• 2009

In order to check the validation of LC simulation, 0.7 inch LCOS panel in full-HD resolution was fabricated and used for the electro-optical measurement. Compared the measured data with the calculated data, the averaged difference was 1.72% under 0 ~ +6 V bias on pixel electrode. To improve the optical characteristics of full-HD LCOS panel, the planar structure and trench structures (0.1 um, 0.2 um and 0.3 um-in-depth) between adjacent pixels were investigated with LC simulation. The planar structure showed the higher reflectance and faster reflectance-voltage response time than the trench structure. The optical fill factor and contrast ratio of planar structure were also higher than those of trench structures. As compared 1 um-in-depth trench structure resembled to the real structure with the planar structure, the optical fill factor was improved by 1.15% and the contrast ratio was improved by 5.26%. In order to minimize the loss of luminance and contrast ratio, the planar structure need to be applied between adjacent pixels.

• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.750-757
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• 2002

A new lateral trench LTEIGBT with p+ diverter was proposed to suppress latch-up of LTIGBT The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEICBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occured at an anode current density of 540A/$\textrm{cm}^2$. In addition, the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. The forward blocking voltage of the conventional LTIGBT of the same size was no more than 105V, We fabricated the proposed LTEIGBT with a p+ diverter after the device and process simulation was finished. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90㎃ and 70㎃, respectively, at the same breakdown voltage of 150V.

• Transactions on Electrical and Electronic Materials
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• 제4권2호
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• pp.15-19
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• 2003

In this paper, the new dual trench gate Emitter Switched Thyristor (DTG-EST) is proposed for improving snap-back effect which leads to a lot of serious problems of device applications. Also the parasitic thyristor that is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The conventional EST exhibits snap-back with the anode voltage and current density 2.73V and 35A/$\textrm{cm}^2$, respectively. But the proposed DTG-EST exhibits snap-back with the anode voltage and current density 0.96V and 100A/$\textrm{cm}^2$, respectively.

• 한국전기전자재료학회논문지
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• 제23권3호
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• 한국분말재료학회지
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• 제20권2호
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• pp.120-124
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• 2013

This study is carried out to develop the new process for the fabrication of ultra-fine electrodes on the flexible substrates using superhydrophobic effect. A facile method was developed to form the ultra-fine trenches on the flexible substrates treated by plasma etching and to print the fine metal electrodes using conductive nano-ink. Various plasma etching conditions were investigated for the hydrophobic surface treatment of flexible polyimide (PI) films. The micro-trench on the hydrophobic PI film fabricated under optimized conditions was obtained by mechanical scratching, which gave the hydrophilic property only to the trench area. Finally, the patterning by selective deposition of ink materials was performed using the conductive silver nano-ink. The interface between the conductive nanoparticles and the flexible substrates were characterized by scanning electron microscope. The increase of the sintering temperature and metal concentration of ink caused the reduction of electrical resistance. The sintering temperature lower than $200^{\circ}C$ resulted in good interfacial bonding between Ag electrode and PI film substrate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• 한국전기전자재료학회논문지
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• 제21권10호
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• pp.885-888
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• 2008

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

• 대한기계학회논문집B
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• 제41권6호
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• pp.423-427
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• 2017

본 논문은 silicon-on-glass(SOG) 공정에서 접합력 균일도 향상을 위한 고정단 설계에 대한 내용을 다룬다. SOG 공정은 전극이 형성된 유리 기판층과 실리콘 구조층의 양극접합을 기반으로 하며, 가속도 센서와 공진형 센서를 비롯한 고종횡비 구조를 갖는 다양한 실리콘 센서들의 제작에 널리 사용된다. 본 논문에서는 전극과 유리 기판층의 표면 사이에 발생하는 단차로 인한 불균일한 접합을 방지하기 위해, 실리콘 구조층에서 유리 기판층과 접합되는 부분과 전극과 겹쳐지는 부분을 트렌치(trench)를 이용해 분리하는 새로운 형상의 고정단을 제안한다. 본 고정단은 추가적인 공정 없이 기존의 SOG 공정으로 제작되는 디바이스들에 손쉽게 적용이 가능하다.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.546-551
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• 2009

In this paper, we describe a self-aligned fabrication method for a nano-patterned bottom electrode using flood exposure from the backside. Misalignments between layers could cause the final devices to fail after the fabrication of the nano-scale bottom electrodes. A self-alignment was exploited to embed the bottom electrode inside the glass substrate. Aluminum patterns act as a dry etching mask to fabricate glass trenches as well as a self-aligned photomask during the flood exposure from the backside. The patterned photoresist (PR) has a negative sidewall slope using the flood exposure. The sidewall slopes of the glass trench and the patterned PR were $54.00^{\circ}$ and $63.47^{\circ}$, respectively. The negative sidewall enables an embedment of a gold layer inside $0.7{\mu}m$ wide glass trenches. Gold residues on the trench edges were removed by the additional flood exposure with wet etching. The sidewall slopes of the patterned PR are related to the slopes of the glass trenches. Nano-scale bottom electrodes inside the glass trenches will be used in beam resonators operating at high resonant frequencies.