• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.79-82
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.

• Journal of Power Electronics
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• v.16 no.2
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• pp.778-785
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• 2016

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

• Journal of Power Electronics
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• v.13 no.4
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• pp.729-736
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• 2013

Knowledge of a power semiconductor's operating temperature is important in circuit design and converter control. Designing appropriate circuitry that does not affect regular circuit operation during virtual junction temperature measurement at actual operating conditions is a demanding task for engineers. The proposed method enables virtual junction temperature estimation with a dedicated modified gate driver circuit based on real-time measurement of a semiconductor's quasi-threshold voltage. A simulation was conducted before the circuit was designed to verify the concept and to determine the basic properties and potential drawbacks of the proposed method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.163-166
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• 2003

The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2\;and\;Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.9
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• pp.523-526
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• 2016

This paper was researched about 1,200 V level floating island IGBT (insulated gate bipolar transistor). Presently, 1,200 V level IGBT is used in Inverter for distributed power generation. We analyzed and compared electrical charateristics of the proposed floating island IGBT and conventional IGBT. For analyzing and comparison, we used T-CAD tool and simulated the electrical charateristics of the devices. And we extracted optimal design and process parameter of the devices. As a result of experiments, we obtained 1,456 V and 1,459 V of breakdown voltages, respectively. And we obatined 4.06 V and 4.09 V of threshold voltages, respectively. On the other hand, on-state voltage drop of floating island IGBT was 3.75 V. but on-state vlotage drop of the conventional IGBT was 4.65 V. Therefore, we almost knew that the proposed floating island IGBT was superior than the conventional IGBT in terms of power dissipation.

• Journal of Power Electronics
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• v.19 no.2
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• pp.413-430
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• 2019

This paper presents an optimum hybrid SVPWM technique for three-level voltage source inverters (VSIs). The proposed hybrid SVPWM technique aims to minimize total harmonic distortion (THD). A new parameter is introduced to incorporate the heterogeneous nature of switching sequences of SVPWM technique. The proposed hybrid SVPWM technique is implemented on a low-cost PIC microcontroller (PIC18F452) and verified experimentally with a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI. Optimum switching sequence results in the three-level inverter configuration are demonstrated. The proposed hybrid SVPWM technique improves the THD performance by 17.3% compared with the best available three-level SVPWM technique.

• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• Journal of Semiconductor Engineering
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• v.1 no.3
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.60.2-60.2
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• 2011

본 연구에서는 Indium-free 및 gallium-free 기반의 산화물 TFT를 제작하기 위해 n-type $TiO_2$ 반도체 기반의 thin film transistor ($Mo/TiO_{2-x}/SiO_2/p+\;+Si$)를 oxygen deficient black $TiO_{2-x}$ 타겟을 이용하여 DC magnetron sputtering 공법으로 제작하고 그 특성을 분석하였다. DC magnetron sputtering 공법으로 성막된 $TiO_{2-x}$ semiconductor의 전기적, 광학적, 화학적 결합 에너지 및 구조적 특성 분석을 위해 semiconductor parameter analyzer (Aglient 4156-C), UV/Vis spectrometer, X-ray Photoelectron Spectroscopy, Transmission Electron Microscopy를 각각 이용하여 분석하였으며 이를 RTA 전/후 특성 비교를 통하여 관찰하였다. $TiO_{2-x}$ TFT의 소자 특성은 RTA 열처리 전/후 전형적인 insulator 특성에서 semiconductor 특성으로 변화되는 것을 관찰할 수 있었으며, 최적화된 열처리 공정에서 filed effect mobility 0.69 $cm^2$/Vs, on to off current ratio $2.04{\times}10^7$, sub-threshold swing 2.45 V/decade와 Vth 10.45 V를 확보할 수 있었다. 또한 RTA 열처리 후 밴드갭이 3.25에서 3.41로 확장되는 특성을 나타내었다. 특히 RTA 열처리 후 stoichiometric $TiO_2$ 상태와는 다른 $Ti^{2+}$, $Ti^{3+}$, $Ti^{4+}$ 등의 다양한 oxidation states가 관찰되었으며 이러한 oxidation states를 $TiO_{2-x}$ 박막에서의 oxygen deficient 상태와 연관시킴으로써 oxygen vacancy의 n-type dopant로의 거동을 확인하였다. $TiO_2$ 채널 기반의 TFT 특성을 통하여서 indium free 또는 gallium free 산화물 채널로써의 가능성을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.