• Title/Summary/Keyword: total execution time

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A Study on Application of Systems Engineering Approach to Design of Smart Manufacturing Execution System (스마트 제조 실행 시스템 기본설계를 위한 시스템 엔지니어링 적용 방법에 대한 연구)

  • Jeon, Byeong-woo;Shin, Kee-Young;Hong, Dae-Geun;Suh, Suk-Hwan
    • Journal of the Korean Society of Systems Engineering
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    • v.11 no.2
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    • pp.95-105
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    • 2015
  • Manufacturing Execution System(MES) is in charge of manufacturing execution in the shop floor based on the inputs given by high level information such as ERP, etc. The typical MES implemented is not tightly interconnected with shop floor control system including real (or near real) time monitoring and control devices such as PLC. The lack of real-time interfaces is one of the major obstacles to achieve accurate and optimization of the total performance index of the shop floor system. Smart factory system in the paradigm of Industry 4.0 tries to solve the problems via CPS (Cyber Physical System) technology and FILS (Factory In-the-Loop System). In this paper, we conducted Systems Engineering Approach to design an advanced MES (namely Smart MES) that can accommodate CPS and FILS concept. Specifically, we tailored Systems Engineering Process (SEP) based on an International Standard formalized as ISO/IEC 15288 to develop Stakeholders' Requirements (StR), System Requirements (SyR). The deliverables of each process are modeled and represented by the SysML, UML customized to Systems Engineering. The results of the research can provide a conceptual framework for future MES that can play a crucial role in the Smart Factory.

A Study on the Efficient Task Scheduling by the Reconstructed Task Graph (태스크 그래프의 재구성에 의한 효율적 태스크 스케줄링에 관한 연구)

  • Byun, Seung-Hwan;Yoo, Kwan-Jong
    • The Transactions of the Korea Information Processing Society
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    • v.4 no.9
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    • pp.2235-2246
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    • 1997
  • This paper presents an effective heuristic task scheduling algorithm for multiprocessor systems. To execute task scheduling effectively which is defined as an allocation of m's tasks onto n's processors(m > n), several problems almost at NP-hard should be cleaned up. The purpose of the task scheduling obtains the minimum execution time by mapping the tasks on a system topology or reduces the total execution time to give a minimum system topology. In order to solve this problem, in this paper, the task scheduling is done by redefining a task graph to a reconstructed task graph (RTG). An RTG is obtained by merging or copying nodes to equal the number of nodes on each level of the task graph to the number of processors of the system topology and then directly scheduled to the system topology. This method obtains a fast scheduling time and a simple scheduling method, and near-optimal execution time without executing steps such as the refinement step and the duplication step after the task scheduling.

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Distributed Computing Models for Wireless Sensor Networks (무선 센서 네트워크에서의 분산 컴퓨팅 모델)

  • Park, Chongmyung;Lee, Chungsan;Jo, Youngtae;Jung, Inbum
    • Journal of KIISE
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    • v.41 no.11
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    • pp.958-966
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    • 2014
  • Wireless sensor networks offer a distributed processing environment. Many sensor nodes are deployed in fields that have limited resources such as computing power, network bandwidth, and electric power. The sensor nodes construct their own networks automatically, and the collected data are sent to the sink node. In these traditional wireless sensor networks, network congestion due to packet flooding through the networks shortens the network life time. Clustering or in-network technologies help reduce packet flooding in the networks. Many studies have been focused on saving energy in the sensor nodes because the limited available power leads to an important problem of extending the operation of sensor networks as long as possible. However, we focus on the execution time because clustering and local distributed processing already contribute to saving energy by local decision-making. In this paper, we present a cooperative processing model based on the processing timeline. Our processing model includes validation of the processing, prediction of the total execution time, and determination of the optimal number of processing nodes for distributed processing in wireless sensor networks. The experiments demonstrate the accuracy of the proposed model, and a case study shows that our model can be used for the distributed application.

A Workflow Scheduling Technique Using Genetic Algorithm in Spot Instance-Based Cloud

  • Jung, Daeyong;Suh, Taeweon;Yu, Heonchang;Gil, JoonMin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.9
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    • pp.3126-3145
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    • 2014
  • Cloud computing is a computing paradigm in which users can rent computing resources from service providers according to their requirements. A spot instance in cloud computing helps a user to obtain resources at a lower cost. However, a crucial weakness of spot instances is that the resources can be unreliable anytime due to the fluctuation of instance prices, resulting in increasing the failure time of users' job. In this paper, we propose a Genetic Algorithm (GA)-based workflow scheduling scheme that can find the optimal task size of each instance in a spot instance-based cloud computing environment without increasing users' budgets. Our scheme reduces total task execution time even if an out-of-bid situation occurs in an instance. The simulation results, based on a before-and-after GA comparison, reveal that our scheme achieves performance improvements in terms of reducing the task execution time on average by 7.06%. Additionally, the cost in our scheme is similar to that when GA is not applied. Therefore, our scheme can achieve better performance than the existing scheme, by optimizing the task size allocated to each available instance throughout the evolutionary process of GA.

The Software Reliability Growth Models for Software Life-Cycle Based on NHPP

  • Nam, Kyung-H.;Kim, Do-Hoon
    • The Korean Journal of Applied Statistics
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    • v.23 no.3
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    • pp.573-584
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    • 2010
  • This paper considers the differences in the software execution environments in the testing phase and the operational phase to determine the optimal release time and warranty period of software systems. We formulate equations for the total expected software cost until the end of the software life cycle based on the NHPP. In addition, we derive the optimal release time that minimizes the total expected software cost for an imperfect debugging software reliability model. Finally, we analyze the sensitivity of the optimal testing and maintenance design related to variation of the cost model parameters based on the fault data observed in the actual testing process, and discuss the quantitative properties of the proposed model.

A Task Scheduling Algorithm with Environment-specific Performance Enhancement Method (환경 특성에 맞는 성능 향상 기법을 사용하는 태스크 스케줄링 알고리즘)

  • Song, Inseong;Yoon, Dongsung;Park, Taeshin;Choi, Sangbang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.5
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    • pp.48-61
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    • 2017
  • An IaaS service of a cloud computing environment makes itself attractive for running large scale parallel application thanks to its innate characteristics that a user can utilize a desired number of high performance virtual machines without maintenance cost. The total execution time of a parallel application on a high performance computing environment depends on a task scheduling algorithm. Most studies on task scheduling algorithms on cloud computing environment try to reduce a user cost, and studies on task scheduling algorithms that try to reduce total execution time are rarely carried out. In this paper, we propose a task scheduling algorithm called an HAGD and a performance enhancement method called a group task duplication method of which the HAGD utilizes. The group task duplication method simplifies previous task duplication method, and the HAGD uses the group task duplication method or a task insertion method according to the characteristics of a computing environment and an application. We found that the proposed algorithm provides superior performance regardless of the characteristics in terms of normalized total execution time through performance evaluations.

An Improved Adaptive Job Allocation Method for Multiprocessor Systems (다중처리기 시스템을 위한 적응적 작업할당 방법의 개선)

  • Ok, Gi-Sang;Park, Jun-Seok;Lee, Won-Ju;Jeon, Chang-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.6
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    • pp.1502-1510
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    • 1999
  • In adaptive job allocation method for multiprocessor systems a job is folded, or split in two halves, to fit for an available subcube in order to reduce the waiting time of jobs. In this method, however, since a job is folded whenever a subcube with the proper size is not found, the prolonged execution time caused by job split may override the savings in waiting time, in which case the total adaptive jobs may be increased. In this paper, an improved adaptive job allocation algorithm, called Estimate-fold allocation, Is presented and evaluated. The proposed algorithm estimates the costs and takes the better of two alternatives ; folding right away and waiting until a bigger subcube becomes available. The average total job execution cost of our algorithm is calculated and compared to those of the conventional adaptive, buddy, and gray-code algorithms through simulations. The results shows that our proposed algorithm performs better than others.

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Performance Analysis of Caching Instructions on SVLIW Processor and VLIW Processor (SVLIW 프로세서와 VLIW 프로세서의 명령어 캐싱에 따른 성능 분석)

  • Ji, Sung-Hyun;Park, No-Kwang;Kim, Suk-Il
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.101-110
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    • 1997
  • SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

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Stepwise Refinement Data Path Synthesis Algorithm for Improved Testability (개선된 테스트 용이화를 위한 점진적 개선 방식의 데이타 경로 합성 알고리즘)

  • Kim, Tae-Hwan;Chung, Ki-Seok
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.6
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    • pp.361-368
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    • 2002
  • This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

Transform Nested Loops into MultiThread in Java Programming Language for Parallel Processing (자바 프로그래밍에서 병렬처리를 위한 중첩 루프 구조의 다중스레드 변환)

  • Hwang, Deuk-Young;Choi, Young-Keun
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.8
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    • pp.1997-2012
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    • 1998
  • It is necessary to find out the parallelism in tlle sequential Java program to execute it on the parallel machine. The loop is a fundamental source to exploit parallelism as it process a large portion of total execution time in sequential Java program on the parallel machine. However, a complete parallel execution can hardly be achieved due to data dependence. This paper proposes the method of exploiting the implicit parallelism by structuring a dependence graph through the analysis of data dependence in the existing Java programming language having a nested loop structure. The parallel code generation method through the restructuring compiler and also the translation method of Java source program into multithread statement. which is supported by the Java programming language itself, are proposed here. The perforance evaluatlun of the program translaed into the thread statement is conducted using the trip cunt of loop and the trip Count of luop and the thread count as parameters The resttucturing compiler provides efficient way of exploiting parallelism by reducing manual overhead conveliing sequential Java program into parallel code. The execution time for the Java program as a result can be reduced un the parallel machine.

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