Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
권호 표지

Stepwise Refinement Data Path Synthesis Algorithm for Improved Testability

개선된 테스트 용이화를 위한 점진적 개선 방식의 데이타 경로 합성 알고리즘

  • Kim, Tae-Hwan (Dept. of Electronic Computer Science, Korea Advanced Institute of Science and Technology) ;
  • Chung, Ki-Seok (Dept. of Computer Engineering, Hongik University)
  • 김태환 (한국과학기술원 전자전산학과) ;
  • 정기석 (홍익대학교 컴퓨터공학과)
  • Published : 2002.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

본 논문은 세 가지 중요한 설계 기준인 테스트 용이화, 설계 면적, 및 전체 수행 시간을 동시에 고려한 새로운 데이터 경로 합성 알고리즘을 제시한다. 우리는 테스트 용이화를 위한 선행 연구들에서 제시한 세 가지 기초적 척도들에 근거하여 새로운 테스트 용이화의 우수성에 대한 척도를 정의한다. 이 척도를 이용하여, 스케쥴링과 할당의 통합된 형태의, 단계식이며 점진적 개선을 통한, 합성 알고리즘을 제시한다. 벤치마크 설계와 다른 회로의 예를 통한 실험에서, 우리는 설계 면적과 수행 시간에 대해 매우 적은 추가 부담으로, 회로의 테스트 용이화가 향상됨을 보인다.

Keywords

References

  1. C. A. Papachristou, S. Chju, and H. Harmanani, 'Data Path Synthesis Method for Self-Testable Designs,' Proc. Design Automation Conference, pp.378-384, 1991 https://doi.org/10.1145/127601.127698
  2. C. A. Papachristou, 'Rescheduling Transformation for High Level Synthesis,' Proc. International Symposium on Circuits and Systems, pp.766-769, 1989 https://doi.org/10.1109/ISCAS.1989.100463
  3. I. Parulkar, S. Gupta, and M. A. Breuer, 'Data path allocation for synthesizing RTL designs with Low BlST area overhead,' Proc. Design Automation Conference, pp.395-401, 1995 https://doi.org/10.1145/217474.217561
  4. I. Parulkar, S. Gupta, and M. A. Breuer, 'Introducing Redundant Computations in a Behavior for Reducing BIST Resources,' Proc. Design Automation Conference, pp.548-553, 1998 https://doi.org/10.1145/277044.277191
  5. I. Parulkar, S. Gupta, and M. A. Breuer, 'Scheduling and Module Assignment for Reducing BIST Resources,' Proc. Design, Automation and Test in Europe, pp. 66-73 1998 https://doi.org/10.1109/DATE.1998.655838
  6. A. Mujumdar, K. Saluja, and R. Jain, 'Incorporating Performance and Testability Constraints during Binding in High-level Synthesis,' IEEE Trans. on CAD, Vol.15, No.10, October 1996 https://doi.org/10.1109/43.541441
  7. L. Avra, 'Allocation and Assignment in High-Level Synthesis for Self-testable Data Paths,' Proc. International Test Conference, pp.463-472, 1991
  8. T-C. Lee, W. H. Wolf, and N. K. Jha, 'Behavioral Synthesis for Easy Testability in Data Path Scheduling,' Proc. International Conference on Computer-Aided Design, pp.616-619, 1992 https://doi.org/10.1109/ICCAD.1992.279303
  9. T-C. Lee et al., 'Behavioral Synthesis for Easy Testability in Data Path Allocation,' Proc. International Conference on Computer Design, pp.29-32, 1992
  10. F. J. Kurdahi and A. C. Parker, 'REAL: A Program for Register Allocation,' Proc. 24th Design Automation Conference, pp.210-215, 1987 https://doi.org/10.1145/37888.37920
  11. L. Stok, 'An Exact Polynomial Time Algorithm for Module Allocation,' Proc. The fifth Int. Workshop on High-Level Synthesis, pp.69-76, 1991
  12. E. M. Sentovich, et al., 'Sequential Circuit Design using Synthesis and Optimization,' Proc. International Conference on Computer Design, pp.328-333, 1992 https://doi.org/10.1109/ICCD.1992.276282
  13. A. Ghosh, S. Devadas, A. R. Newton, 'Test Generation for Highly Sequential Circuits,' Proc. International Conference on Computer-Aided Design, pp.362-365, 1989 https://doi.org/10.1109/ICCAD.1989.76970