• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of Environmental Science International
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• v.28 no.1
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• pp.125-135
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• 2019

For the purposes of enhancing usability of Numerical Weather Prediction (NWP), the quantitative precipitation prediction scheme by machine learning has been proposed. In this study, heavy rainfall was corrected for by utilizing rainfall predictors from LENS and Radar from 2017 to 2018, as well as machine learning tools LightGBM and XGBoost. The results were analyzed using Mean Absolute Error (MAE), Normalized Peak Error (NPE), and Peak Timing Error (PTE) for rainfall corrected through machine learning. Machine learning results (i.e. using LightGBM and XGBoost) showed improvements in the overall correction of rainfall and maximum rainfall compared to LENS. For example, the MAE of case 5 was found to be 24.252 using LENS, 11.564 using LightGBM, and 11.693 using XGBoost, showing excellent error improvement in machine learning results. This rainfall correction technique can provide hydrologically meaningful rainfall information such as predictions of flooding. Future research on the interpretation of various hydrologic processes using machine learning is necessary.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.171-174
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• 2002

This paper presents an implementation method of phasor measurement device, which is based on the FPGA implementation of the sliding-DFT The design is verified by the timing simulation of its operation. The error effect of coefficient approximation and frequency deviation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.8-13
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• 2009

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.3
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• pp.112-119
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• 1982

An experimental 2400bps modem emlpoying 4-phase DPSK in compliance with the CCITT recommendation V.26 is developed. Integrated circuits are used throughtout the circuit implementation, including active filters and a semiconductor delay line. A new timing recovery scheme is proposed and adopted successfully. The error rate perfromance is found to be in fair agreement with the theoretical prediction.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.687-694
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• 1999

In this paper, to draw out the parameter of synchronization for ADSL(Asymmetric Digital Subscriber Line) chip design, we analyze the performance of STR(Symbol Timing Recovery) and frame synchronization with computer simulation. We analyze and design PLL(Phase Lock Loop) loop for ADSL. As a result, we obtained the optimum parameter of STR to design ADSL chip. Also, when performed frame synchronization with several algorithm, we analyzed the performance of FER(Frame Error Rate) and the effect of frame offset with computer simulation.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.1-6
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• 1997

The scheduling problem of satisfying both 0/1 constraint and the timing constraint while minimizing the total error is NP-complete when the optional parts have arbitrary processing times. In this paper, we present a heuristic scheduling algorithm for 0/1 constraint imprecise systems which consist of communicating tasks running on multiple processors. The algorithm is based on the program graph which is similar to the one presented in[4]. To check the schedulability, we apply Lawler and Moore's theorem. To analyze the performance of the proposed algorithm, intensive simulation is done. The results of the simulation shows that the longest processing first selection strategy outperforms random or minimal laxity policies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.10
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• pp.829-841
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• 1990

On assuming that the transmission speed of the original information is the fifth-order transmission speed of the Korea digital multiplex hierarchy (564.992Mb/s), this paper proposes a new structure of the transmission line frame at the terminal repeater system, in order to not only maintain and conserve 565Mb/s optical fiber transmission system but also make the B.S.I. of digital communication network for the optical transmission. And the structure uses the mBIZ transmission line code, which is considered the optimal transmission line code of conventional transmission line codes. System hardware of the transmission line frame structure proposed in this paper is consisted by a method of pulse stuffing after converting the speed of the original information signal sequence at the terminal repeater system for 565Mb/s optical transmission. As a result of this, we can prevent the optical transmission system from a domino phenomenon, the phenomenon of the continuous error multiplication of systems by the transmission error, and suppress timing jitter and the identical consecutive digit number. And also we can improve SNR of the optical transmission system about 2dB because of raising total BER at the optical terminal system up to 10.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.47-54
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• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.