• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.581-584
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• 2003

It is important to know phase offsets of PN (Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to make a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration far an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time of the proposed synchronization method is derived analytically, and we see that the method acquires very fast acquisition in the high SNR (Signal-to- Noise Ratio) environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.809-818
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• 2002

In this paper, we propose a fast cell search algorithm keeping compatible with the standard cell search algorithm of the WCDMA system. The proposed algorithm can acquire the synchronization of slot and frame times, and the code group identification using only one synchronization channel while the standard algorithm employs two synchronization channels called P-SCH and S-SCH. The proposed synchronization channel structure is the same as the P-SCH structure of the WCDMA system. However, the P-SCH is modulated with a specific polarization code, which is one element of new code group codes. The proposed algorithm can reduce both the BS' transmission power and the complexity of receiver as compared with the conventional one since only on synchronization channel is used. It is shown through the computer simulation that the proposed algorithm yields a significant improvement in terms of cell search time compared with the standard especially in low SNR environments.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.3
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• pp.266-273
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• 2016

In this paper, we propose the signal processing techniques for the command link receiver mounted to aircrafts flying at a high speed. In order to acquire the various information transmitted from ground through radio frequency links, the wide received signal range must be guaranteed as well as the carrier synchronization and symbol synchronization be performed correctly within short pulse sections. After the synchronization step, we should be able to achieve theoretical performance of the modulation and demodulation scheme applied as deciding bit and symbol at the time appointed. By test results, we make sure that the proposed signal processing techniques can be effectively applied command link receiver mounted to aircrafts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.469-479
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• 2009

The GEM frame is used a mean to deliver the variable length user data and consists of the header and the payload in the G-PON system. The HEC field of header protects contents of the header and is used to maintain GEM frame synchronization at the same time. When an LCDG (Loss of GEM Channel Delineation) occurs while receiving frames, the receiver have to discard corrupted frames until acquiring the synchronization again. Accordingly, high-speed synchronization method is required to minimize the frame loss. In this paper, we suggest not only a main state machine but a sub-state machine to reduce the frame loss when undetectable errors occurred in the GEM header. Also, we provide a more efficient and fast parallel structure to detect the starting point of the header. Finally, the proposed method is implemented with the FPGA and verified by the logic analyzer.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.136-141
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• 2007

The frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) for applications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the telecom network. As telecom networks evolve from circuit to packet switching, proper synchronization algorithm should be meditated for IP networks to achieve performance quality comparable to that of legacy circuit-switched networks. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. But, The ToP can be affected by impairments of a network such as packet delay variation. This paper proposes the efficient method to minimize the expectable delay variation when ToP synchronizes the distributed clocks. The simulation results are presented to demonstrate the improved performance case when the efficient ToP transmit algorithm is applied.

• Journal of Broadcast Engineering
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• v.24 no.7
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• pp.1259-1265
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• 2019

Maintaining timing relationships among packets in a single media stream or between packets from different media streams is an essential criterion in MMT system. It is the function of the synchronization and de-jittering algorithms to re-adjust timing relationship between the MMT packets to assure synchronized playback. Thus, delivery of time constrained MPEG media on time, according to their temporal requirements, is an important goal of MMT. For this purpose MMT needs to specify syntax and semantics of a timing model to be used by the delivery functions. In this paper, we propose a proper timestamp-related header format for MMT delivery timing model to support media synchronization in various delivery scenarios including hybrid delivery.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.07a
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• pp.69-72
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• 2013

본 논문은 TPSN 알고리즘의 시각 동기화 오차를 개선하기 위하여 Imote2 센서 노드의 클럭 드리프트 특성을 적용하는 개선된 TPSN 알고리즘을 제안한다. 클럭 드리프트의 원인은 주로 수정발진기에 기인한다. 본 연구에서는 온도 및 습도 등 환경 조건이 비슷할 경우에 드리프트가 크게 차이나지 않는다는 실험 결과에 따라 드리프트의 평균값을 구하고 이를 TPSN 동기화 오차 보정에 사용한다. 이때 적용되는 드리프트 특성 값은 센서 노드 설치 이전에 미리 측정하여야 한다. 실험을 통하여 본 논문에서 제안한 개선된 TPSN 알고리즘이 동기화 오차 개선에 효과적임을 확인하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.40-47
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• 1998

This paper presents the physiological signal processing CMOS one chip for transmitting human bodys small electrical signals such as electrocardiogram(EKG) or electromyogram(EMG) and the external system for receiving signals was implemented by the commercial ICs. For simultaneous four-subject four-channel telemetry, a new enfored synchronization techniqeu using infrared bi-directional communication has been proposed. The telemeter IC with the size of 5.1*5.1mm$^{2}$ has the following functions: receiving of command signal, initialization of internal state of all functional blocks, decoding of subject-selection signal, time multiplexing of 4-channel modulated physiological signals, transmitting of telemetry signal to external system and auto power down control. The newly designed synchronized oscillator with low supply voltage dependence in the telemeter IC operates at a supply voltage from 4.6~6.0V and the nonlinearity error of PIM modulator was less than 1.2%F.S(full scale). The power saving block operates at the period of 2.5ms even if the telemetry IC does not receive command signal from external system for a constant time.

• Journal of The Korean Astronomical Society
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• v.51 no.1
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• pp.1-4
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• 2018

We study the pseudo-synchronous orbital motion of a binary system on the main sequence. The equations of the pseudo-synchronous orbit are derived up to $O(e^4)$ where e is the eccentricy of the orbit. We integrate the equations to present their solutions. The theoretical results are applied to the evolution of the orbit and spin of the binary star Y Cygni, which has a current eccentricity of $e_0\;=\;0.142$. We tabulate our numerical results for the evolution of the orbit and spin per century. The numerical results for the semi-major axes and rotational angular velocities in the evolutional time scales of three stages (synchronization, circularization, and collapse time scale) are also tabulated. Synchronization is achieved in about $5{\times}10^3\;years$ followed by circularization lasting about $1{\times}10^5\;years$ before decaying in $2{\times}10^5\;years$.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.634-638
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• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.