• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1494-1495
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• 2009

Thin Film Transistor(TFT) having CIS (CuInSe) semiconductor layer was fabricated and characterized. Heavily doped Si was used as a common gate electrode and PECVD Silicon nitride ($SiN_x$) was used as a gate dielectric material for the TFT. Source and drain electrodes were deposited on the $SiN_x$ layer and CIS layer was formed by a direct patterning method between source and drain electrodes. Nanoparticle of CIS material was used as the ink of the direct patterning method.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.12
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• pp.559-561
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• 2003

We report a new excimer laser annealing method which successfully results in a single grain boundary formation in the channel of polycrystalline silicon thin film transistor. The proposed method is based on lateral grain growth and employs aluminum patterns which act as selective beam mask and lateral heat sink. The maximum grain size obtained by the proposed method is about 1.6${\mu}{\textrm}{m}$ in the length. The grainboundaries should be arranged parallel with the direction of current flow for the best device performance, so we propose a new device fabrication method and a new poly-Si TFT structure. Poly-Si TFT fabricated by the proposed method exhibits considerably improved electrical characteristics, such as high field effect mobility exceeding 240 $cm^2$/Vsec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.9
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• pp.844-847
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• 2008

The photo leakage currents of a conventional hydrogenated amorphous silicon(a-Si:H) thin film transistor(TFT) were investigated and analyzed in case of illumination from various light sources such as halogen lamp, cold cathode fluorescent lamp(CCFL) backlight, and white light emitting diode(LED) backlight. The photo leakage characteristics showed the apparent differences in the leakage level and in the $I_{on}/I_{off}$ ratio in spite of the similar luminances of light sources. This leakage level is expected to be related to the wavelength of the lowest intensity peak from the spectral characteristics of light sources.

• ETRI Journal
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• v.34 no.6
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• pp.966-969
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• 2012

From a practical viewpoint, the topic of electrical stability in oxide thin-film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium-gallium-zinc-oxide (IGZO)-TFTs have revealed that an IGZO-TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X-ray photoelectron spectroscopy analysis.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.7
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• pp.525-531
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• 2011

In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.

• Information Display
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• v.7 no.2
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• pp.10-13
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• 2006

Active Matrix Flat Panel Display(AM-FPD)의 경쟁력 향상을 위해서 반드시 필요한 고성능, 고생산성 Thin Film Transistor(TFT)를 제작에 사용하는 결정화 방법 중, 산업화에 가장 근접한 레이저 결정화 방법 및 장비에 대해서 기술한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.471-471
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• 2013

Highly stable and high performance amorphous oxide semiconductor thin film transistors (TFTs) were fabricated using 4-mercaptophenol (4MP) doped ZnO by atomic layer deposition (ALD). The 4 MP concentration in ZnO films were varied from 1.7% to 5.6% by controlling Zn: 4MP pulses. The carrier concentrations in ZnO thin films were controlled from $1.017{\times}10^{20}$/$cm^3$ to $2,903{\times}10^{14}$/$cm^3$ with appropriate amount of 4MP doping. The 4.8% 4MP doped ZnO TFT revealed good device mobility performance of $8.4cm^2V-1s-1$ and on/off current ratio of $10^6$. Such 4MP doped ZnO TFTs were stable under ambient conditions for 12 months without any apparent degradation in their electrical properties. Our result suggests that 4 MP doping can be useful technique to produce more reliable oxide semiconductor TFT.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.110.1-110.1
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• 2012

Recently, advances in ZnO based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). However, the electrical performances of oxide semiconductors are significantly affected by interactions with the ambient atmosphere. Jeong et al. reported that the channel of the IGZO-TFT is very sensitive to water vapor adsorption. Thus, water vapor passivation layers are necessary for long-term current stability in the operation of the oxide-based TFTs. In the present work, $Al_2O_3$ and $TiO_2$ thin films were deposited on poly ether sulfon (PES) and $SnO_x$-based TFTs by electron cyclotron resonance atomic layer deposition (ECR-ALD). And enhancing the WVTR (water vapor transmission rate) characteristics, barrier layer structure was modified to $Al_2O_3/TiO_2$ layered structure. For example, $Al_2O_3$, $TiO_2$ single layer, $Al_2O_3/TiO_2$ double layer and $Al_2O_3/TiO_2/Al_2O_3/TiO_2$ multilayer were studied for enhancement of water vapor barrier properties. After thin film water vapor barrier deposited on PES substrate and $SnO_x$-based TFT, thin film permeation characteristics were three orders of magnitude smaller than that without water vapor barrier layer of PES substrate, stability of $SnO_x$-based TFT devices were significantly improved. Therefore, the results indicate that $Al_2O_3/TiO_2$ water vapor barrier layers are highly proper for use as a passivation layer in $SnO_x$-based TFT devices.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.237-241
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• 2000

The structural, electrical and etching characteristics of Al alloy thin film with low impurity concentrations AlNd deposited by using do magnetron sputtering deposition are investigated for the applications as gate bus line in the TFt-LCD panel. And ITO thin film was deposited on AlNd, then the contact resistance was measured by Kelvin resistor. The deposited thin films show the decrease of resistivity and the increase of grain size after the RTA at $300^{\circ}C$ for 20 min. Moreover, the resistivity of AlNd does not show appreciable grain size dependence after RTA. It is concluded that the decrease of resistivity after RTA is due to the increase of grain size. The annealed AlNd is found to be hillock free. The etching profiles of AlNd was good and the minimun contact resistance was about $110\;{\mu\Omega}cm$. Calculation results reveal that the AlNd (2wt.%) thin film can be applicable to 25" SXGA class TFT-LCD panels.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.