• Communications of the Korean Mathematical Society
• /
• v.36 no.2
• /
• pp.257-266
• /
• 2021

In this paper, by using the sequence of adjointable operators from C^*-algebra 𝓐 into Hilbert 𝓐-module E, the woven frames of multipliers in Hilbert C^*-modules are introduced. Meanwhile, we study the effect of operators on these frames and, also we construct the new woven frame of multipliers in Hilbert 𝓐-module 𝓐. Finally, compositions of woven frames of multipliers in Hilbert C^*-modules are studied.

• Bulletin of the Korean Mathematical Society
• /
• v.58 no.2
• /
• pp.461-479
• /
• 2021

This paper includes a general version of Bessel multipliers in Hilbert C∗-modules. In fact, by combining analysis, an operator on the standard Hilbert C∗-module and synthesis, we reach so-called generalized Bessel multipliers. Because of their importance for applications, we are interested to determine cases when generalized multipliers are invertible. We investigate some necessary or sufficient conditions for the invertibility of such operators and also we look at which perturbation of parameters preserve the invertibility of them. Subsequently, our attention is on how to express the inverse of an invertible generalized frame multiplier as a multiplier. In fact, we show that for all frames, the inverse of any invertible frame multiplier with an invertible symbol can always be represented as a multiplier with an invertible symbol and appropriate dual frames of the given ones.

• Communications of the Korean Mathematical Society
• /
• v.33 no.2
• /
• pp.527-533
• /
• 2018

Let $\mathcal{X}$ be a countably generated Hilbert module over a locally $C^*$-algebra $\mathcal{A}$ in multiplier module M($\mathcal{X}$) of $\mathcal{X}$. We propose the necessary and sufficient condition such that a sequence $\{h_n:n{{\in}}\mathbb{N}\}$ in M($\mathcal{X}$) is a standard frame of multipliers in $\mathcal{X}$. We also show that if T in $b(L_{\mathcal{A}}(\mathcal{X}))$, the space of bounded maps in set of all adjointable maps on $\mathcal{X}$, is surjective and $\{h_n:n{{\in}}\mathbb{N}\}$ is a standard frame of multipliers in $\mathcal{X}$, then $\{T{\circ}h_n:n{\in}\mathbb{N}}$ is a standard frame of multipliers in $\mathcal{X}$, too.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.31-37
• /
• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Korea-Australia Rheology Journal
• /
• v.18 no.4
• /
• pp.171-181
• /
• 2006

We present a short review for authors' previous work on direct numerical simulations for inertialess hard particle suspensions formulated either with a Newtonian fluid or with viscoelastic polymeric fluids to understand the microstructural evolution and the bulk material behavior. We employ two well-defined bi-periodic domain concepts such that a single cell problem with a small number of particles may represent a large number of repeated structures: one is the sliding bi-periodic frame for simple shear flow and the other is the extensional bi-periodic frame for planar elongational flow. For implicit treatment of hydrodynamic interaction between particle and fluid, we use the finite-element/fictitious-domain method similar to the distributed Lagrangian multiplier (DLM) method together with the rigid ring description. The bi-periodic boundary conditions can be effectively incorportated as constraint equations and implemented by Lagrangian multipliers. The bulk stress can be evaluated by simple boundary integrals of stresslets on the particle boundary in such formulations. Some 2-D example results are presented to show effects of the solid fraction and the particle configuration on the shear and elongational viscosity along with the micro-structural evolution for both particles and fluid. Effects of the fluid elasticity has been also presented.

• Earthquakes and Structures
• /
• v.8 no.1
• /
• pp.205-224
• /
• 2015

A new method for designing moment resisting concrete frames failing in a global mode is presented in this paper. Starting from the analysis of the typical collapse mechanisms of frames subjected to horizontal forces, the method is based on the application of the kinematic theorem of plastic collapse. The beam section properties are assumed to be known quantities, because they are designed to resist vertical loads. As a consequence, the unknowns of the design problem are the column sections. They are determined by means of design conditions expressing that the kinematically admissible multiplier of the horizontal forces corresponding to the global mechanism has to be the smallest among all kinematically admissible multipliers. In addition, the proposed design method includes the influence of second-order effects. In particular, second-order effects can play an important role in the seismic design and can be accounted for by means of the mechanism equilibrium curves of the analysed collapse mechanism. The practical application of the proposed methodology is herein presented with reference to the design of a multi-storey frame whose pattern of yielding is validated by means of push-over analysis.

• Wind and Structures
• /
• v.12 no.2
• /
• pp.89-101
• /
• 2009

The Monte Carlo procedure was used to simulate wind load effects on a light-frame low-rise structure of irregular shape and a main wind force resisting system. Two analytical models were studied: rigid-beam and rigid-plate models. The models assumed that roof diaphragms were rigid beam or rigid plate and shear walls controlled system behavior and failure. The parameters defining wall stiffness, including imperfections, were random and included wall stiffness, wall capacity and yield displacements. The effect of openings was included in the simulation via a set of discrete multipliers with uniform distribution. One and two-story buildings were analyzed and the models can be expanded into multiple-floor structures provided that the assumptions made in this paper are not violated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.1
• /
• pp.925-927
• /
• 2005

The study is about a finite field multiplying unit, which performs a calculation t-times as fast as the Mastrovito's multiplier architecture, suggesting and using the 2-times faster multiplier architecture. Former studies on finite field multiplication architecture includes the serial multiplication architecture, the array multiplication architecture, and the hybrid finite field multiplication architecture. Mastrovito's serial multiplication architecture has been regarded as the basic architecture for the finite field multiplication, and in order to exploit parallelism, as much resources were expensed to get as much speed in the finite field array multipliers. The array multiplication architecture has weakness in terms of area/performance ratio. In 1999, Parr has proposed the hybrid multipcliation architecture adopting benefits from both architectures. In the hybrid multiplication architecture, the main hardware frame is based on the Mastrovito's serial multiplication architecture with smaller 2-dimensional array multipliers as processing elements, so that its calculation speed is fairly fast costing intermediate resources. However, as the order of the finite field, complex integers instead of prime integers should be used, which means it cannot be used in the high-security applications. In this paper, we propose a different approach to devise a finite field multiplication architecture using Mastrovito's concepts.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.4
• /
• pp.64-71
• /
• 2009

This paper presents an efficient frame synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation(DVB-S2). To achieve the satisfactory performance under severe channel conditions and the efficient hardware resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can improve the performance of the frame and frequency synchronizer since each block operates jointly in parallel and significantly reduce the complexity of the frame synchronizer. Hence, The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&STM SFU broadcast test equipment and consists of 29,821 LUTs with XilinxTM Virtex IV LX200.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.10
• /
• pp.1-7
• /
• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).