• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Information Systems Review
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• v.3 no.2
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• pp.277-288
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• 2001

Of critical importance to the success of any e-commerce site are the two factors: rapid application development and quick response time. A three-tier architecture composed of presentation layer, business layer, and data access layer emerges to allow rapid changes in user interface, business logic, and database structures. Too often, such a logical three-tier architecture is considered as requiring a three-tier physical architecture: Web server, application server, and database server running on separate computers. Contrary to the common belief, a Web stress test reveals that the three-tier logical architecture implemented on a two-tier physical platform guarantees a quicker response time due to the reduction in cross-machine communications. This would lead business firms to economize their spending on e-commerce: increasing the number of physical servers to expedite transaction is not necessarily the best solution. Before selecting a particular hardware configuration, a Web stress test needs to be conducted to compare the relative merits of alternative physical architectures. Together with capacity planning, Web stress test emerges as a powerful tool to build robust, yet economical e-commerce sites.

• Journal of the Korea Institute of Military Science and Technology
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• v.27 no.2
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• pp.203-212
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• 2024

This paper describes the establishment of defense systems test works architecture model for the efficient operation of an expanded test organization and the provision of standardized test services after the integration of proving grounds in ADD. The system engineering vee model is applied to the defense system test works to define the project management model and the unit-test management model. In order to establish the defense systems test works architecture model, the process flow of test works, artifacts by life cycle, and interrelations between regulations and test works are explained, and Integrated Test Information System for implementation of architecture model is discussed. Through the defense systems test works architecture model presented in this study, it will contribute to quickly responding to the test requirements of complex and diverse defense systems, efficiently managing projects, and providing standardized test services.

• International Journal of Naval Architecture and Ocean Engineering
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• v.13 no.1
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• pp.223-235
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• 2021

The Vortex-Induced Vibration (VIV) test system on deepwater riser based on Bare Fiber Bragg Grating (BFBG) sensor technology was designed. Meanwhile, a riser VIV response numerical model was established based on the work-energy principle. The results show that the first-order vibration frequency dominates the vibration of the riser, and as the velocity increases, the dominant frequency of the riser gradually increases under the effect of different top tensions. At the same velocity, as the top tension increases step by step, the dominant frequency and fatigue damage at the same position along the axial length of the riser both gradually decreases. The model test and numerical simulation show a relatively consistent change, maintaining a high degree of agreement. The process control system based on BFBG of model test has excellent performance, and FBG sensors have great advantages in VIV test of a vertical riser in water.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Nuclear Engineering and Technology
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• v.54 no.3
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• pp.1071-1084
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• 2022

The present study aims to investigate the dynamic properties of a novel isolation system composed of separate rubber and wire isolators. The testing program comprised pure compressive, pure-shear, compressive-stress dependence, and shear-strain dependence tests that used full-scale test specimens according to ISO 22762-1. A total of 22 test specimens were fabricated and investigated. Among the tests, the pure compressive test was a destructive test that reached up to the failure stage, whereas the others were nondestructive tests before the failure stage. Similar to the pure-shear test, at each compressive-stress level in the compressive dependence test or at each shear-strain level in the shear-strain dependence test, the cyclic loading was conducted for three cycles. In the nondestructive tests, examination of the dynamic shear properties in the X-direction was independent of the Y-direction. The test results revealed that the increase in the shear strain increased the energy dissipation but decreased the damping ratio, whereas the increase in the compressive stress increased the damping ratio. In addition, a macro model was developed to simulate the load-displacement response of the isolation systems, and the prediction results were consistent with the experimental results.

• International Journal of Naval Architecture and Ocean Engineering
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• v.13 no.1
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• pp.292-305
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• 2021

The present study concerns uncertainty assessment of powering prediction from towing tank model tests, suggested by the International Towing Tank Conference (ITTC). The systematic uncertainty of towing tank tests was estimated by allowance of test setup and measurement accuracy of ITTC. The random uncertainty was varied from 0 to 8% of the measurement. Randomly generated inputs of test conditions and measurement data sets under systematic and random uncertainty are used to statistically analyze resistance and propulsive performance parameters at the full scale. The error propagation through an extrapolation procedure is investigated in terms of the sensitivity and coefficient of determination. By the uncertainty assessment, it is found that the uncertainty of resultant powering prediction was smaller than the test uncertainty.

• ETRI Journal
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• v.36 no.2
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• pp.293-300
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• 2014

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.